[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)

[Jack Styles via llvm-commits]

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@@ -152,7 +118,7 @@ bool RISCVInitUndef::handleReg(MachineInstr *MI) {
       continue;
     if (!UseMO.getReg().isVirtual())
       continue;
-    if (!isVectorRegClass(UseMO.getReg()))
+    if (!TII->isVectorRegClass(MRI->getRegClass(UseMO.getReg())))
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Stylie777 wrote:

Actually, a second thought @ostannard, is this function needed? This makes sure there is a Pseudo instruction available but if one has not been implemented the issue will still exist for that instruction. 

I propose to remove the function and check all together, this will ensure that when adding support for new architectures, all the register classes that require support have the relevant pseudo instruction added. 

https://github.com/llvm/llvm-project/pull/77770