[llvm] [AArch64][SVE2] Generate urshr rounding shift rights (PR #78374)

[Paul Walker via llvm-commits]

================
@@ -20192,6 +20248,9 @@ static SDValue performIntrinsicCombine(SDNode *N,
   case Intrinsic::aarch64_sve_uqsub_x:
     return DAG.getNode(ISD::USUBSAT, SDLoc(N), N->getValueType(0),
                        N->getOperand(1), N->getOperand(2));
+  case Intrinsic::aarch64_sve_urshr:
+    return DAG.getNode(AArch64ISD::URSHR_I_PRED, SDLoc(N), N->getValueType(0),
+                       N->getOperand(1), N->getOperand(2), N->getOperand(3));
----------------
paulwalker-arm wrote:

This doesn't look sound to me.  Either the naming of the AArch64ISD node is wrong or there needs to be a PatFrags that contains this node and the intrinsic.  I say the because the `_PRED` nodes have no requirement when it comes to the result of inactive lanes where as the `aarch64_sve_urshr` intrinsic has a very specific requirement.

https://github.com/llvm/llvm-project/pull/78374