[llvm] [AArch64][SVE2] Generate urshr rounding shift rights (PR #78374)

[Usman Nadeem via llvm-commits]

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@@ -20895,12 +20983,24 @@ static SDValue performUzpCombine(SDNode *N, SelectionDAG &DAG,
     }
   }
 
+  if (SDValue Urshr = tryCombineExtendRShTrunc(N, DAG))
+    return Urshr;
+
   if (SDValue Rshrnb = trySimplifySrlAddToRshrnb(Op0, DAG, Subtarget))
     return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, Rshrnb, Op1);
 
   if (SDValue Rshrnb = trySimplifySrlAddToRshrnb(Op1, DAG, Subtarget))
     return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, Op0, Rshrnb);
 
+  // uzp1(bitcast(x), bitcast(y)) -> uzp1(x, y)
+  if (isHalvingTruncateAndConcatOfLegalIntScalableType(N) &&
+      Op0.getOpcode() == ISD::BITCAST && Op1.getOpcode() == ISD::BITCAST) {
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UsmanNadeem wrote:

This is the transform:
```
    nxv4i32 = AArch64ISD::UZP1 bitcast(nxv4i32 to nxv2i64), bitcast(nxv4i32 to nxv2i64)
    =>
    nxv4i32 = AArch64ISD::UZP1 nxv2i64, nxv2i64
```

Both get lowered to uzp1.s and removing the bitcast makes the code simpler.

An example here: https://godbolt.org/z/b7hsqc1Ev

I limited it to little endian.

https://github.com/llvm/llvm-project/pull/78374