[llvm] e34fd2e - [CodeGen] Simplify RegisterClassInfo BitVector comparisons. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2024-01-31T16:25:19Z
New Revision: e34fd2e193686f8a98504b58c12d966ce14b4209

URL: https://github.com/llvm/llvm-project/commit/e34fd2e193686f8a98504b58c12d966ce14b4209
DIFF: https://github.com/llvm/llvm-project/commit/e34fd2e193686f8a98504b58c12d966ce14b4209.diff

LOG: [CodeGen] Simplify RegisterClassInfo BitVector comparisons. NFC.

Added: 
    

Modified: 
    llvm/lib/CodeGen/RegisterClassInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index 8869a861de061..b45eb467e61ad 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -96,8 +96,7 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
   for (const MCPhysReg *I = CSR; *I; ++I)
     for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
       CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
-  if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
-      IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
+  if (IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
     Update = true;
     IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;
   }
@@ -106,7 +105,7 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
 
   // Different reserved registers?
   const BitVector &RR = MF->getRegInfo().getReservedRegs();
-  if (Reserved.size() != RR.size() || RR != Reserved) {
+  if (RR != Reserved) {
     Update = true;
     Reserved = RR;
   }