[llvm] [AArch64] Use DAG->isAddLike in add_and_or_is_add (PR #79563)

[David Green via llvm-commits]

https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/79563

>From 2e692c3ab3d3d1b659ba21fcc51fc87d39133f96 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Fri, 26 Jan 2024 09:40:29 +0000
Subject: [PATCH 1/2] [AArch64] Add a test for disjoint or ashr fold. NFC

---
 llvm/test/CodeGen/AArch64/shift-accumulate.ll | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/llvm/test/CodeGen/AArch64/shift-accumulate.ll b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
index 2ca6c73d3b831..cc96aabbb33a1 100644
--- a/llvm/test/CodeGen/AArch64/shift-accumulate.ll
+++ b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
@@ -174,3 +174,14 @@ define <2 x i64> @usra_with_movi_v2i64(<16 x i8> %0, <16 x i8> %1) {
   %7 = or <2 x i64> %6, %5
   ret <2 x i64> %7
 }
+
+define <4 x i16> @usra_v4i16_disjointor(<4 x i16> %a) {
+; CHECK-LABEL: usra_v4i16_disjointor:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushr v1.4h, v0.4h, #7
+; CHECK-NEXT:    orr v0.8b, v1.8b, v0.8b
+; CHECK-NEXT:    ret
+  %s = lshr <4 x i16> %a, <i16 7, i16 7, i16 7, i16 7>
+  %o = or disjoint <4 x i16> %s, %a
+  ret <4 x i16> %o
+}

>From 17bc2271c75e358901b7a1c1ebc22c41d4d83489 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Wed, 31 Jan 2024 16:22:18 +0000
Subject: [PATCH 2/2] [AArch64] Use DAG->isAddLike in add_and_or_is_add

This allows it to work with disjoint or's as well as computing the known bits.
---
 llvm/lib/Target/AArch64/AArch64InstrInfo.td   | 2 +-
 llvm/test/CodeGen/AArch64/arm64-csel.ll       | 3 +--
 llvm/test/CodeGen/AArch64/shift-accumulate.ll | 3 +--
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index da1bec73fbf92..6beacea31cb00 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -899,7 +899,7 @@ def add_and_or_is_add : PatFrags<(ops node:$lhs, node:$rhs),
                          [(add node:$lhs, node:$rhs), (or node:$lhs, node:$rhs)],[{
    if (N->getOpcode() == ISD::ADD)
      return true;
-   return CurDAG->haveNoCommonBitsSet(N->getOperand(0), N->getOperand(1));
+   return CurDAG->isADDLike(SDValue(N,0));
 }]> {
   let GISelPredicateCode = [{
      // Only handle G_ADD for now. FIXME. build capability to compute whether
diff --git a/llvm/test/CodeGen/AArch64/arm64-csel.ll b/llvm/test/CodeGen/AArch64/arm64-csel.ll
index 52fb23d20e8ef..1cf99d1b31a8b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-csel.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-csel.ll
@@ -500,9 +500,8 @@ entry:
 define i64 @selor64_disjoint(i64 %num, i64 %x) {
 ; CHECK-LABEL: selor64_disjoint:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    orr x8, x0, #0x1
 ; CHECK-NEXT:    cmp x1, #0
-; CHECK-NEXT:    csel x0, x8, x0, ne
+; CHECK-NEXT:    cinc x0, x0, ne
 ; CHECK-NEXT:    ret
 entry:
   %tobool.not = icmp ne i64 %x, 0
diff --git a/llvm/test/CodeGen/AArch64/shift-accumulate.ll b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
index cc96aabbb33a1..1daa4ea397c83 100644
--- a/llvm/test/CodeGen/AArch64/shift-accumulate.ll
+++ b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
@@ -178,8 +178,7 @@ define <2 x i64> @usra_with_movi_v2i64(<16 x i8> %0, <16 x i8> %1) {
 define <4 x i16> @usra_v4i16_disjointor(<4 x i16> %a) {
 ; CHECK-LABEL: usra_v4i16_disjointor:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ushr v1.4h, v0.4h, #7
-; CHECK-NEXT:    orr v0.8b, v1.8b, v0.8b
+; CHECK-NEXT:    usra v0.4h, v0.4h, #7
 ; CHECK-NEXT:    ret
   %s = lshr <4 x i16> %a, <i16 7, i16 7, i16 7, i16 7>
   %o = or disjoint <4 x i16> %s, %a