[llvm] d309261 - [llvm][InstCombine] bitcast bfloat half castpair bug (#79832)

[via llvm-commits]

Author: Nashe Mncube
Date: 2024-01-31T11:42:10Z
New Revision: d309261d05cf173e6a18b20be986877fd87fe4f3

URL: https://github.com/llvm/llvm-project/commit/d309261d05cf173e6a18b20be986877fd87fe4f3
DIFF: https://github.com/llvm/llvm-project/commit/d309261d05cf173e6a18b20be986877fd87fe4f3.diff

LOG: [llvm][InstCombine] bitcast bfloat half castpair bug (#79832)

Miscompilation arises due to instruction combining of cast pairs of the
type `bitcast bfloat to half` + `<FPOp> bfloat to half` or `bitcast half
to bfloat` + `<FPOp half to bfloat`. For example `bitcast bfloat to
half`+`fpext half to double` or `bitcast bfloat to half`+`fpext bfloat
to double` respectively reduce to `fpext bfloat to double` and `fpext
half to double`. This is an incorrect conversion as it assumes the
representation of `bfloat` and `half` are equivalent due to having the
same width. As a consequence miscompilation arises.

Fixes #61984

Added: 
    llvm/test/Transforms/InstCombine/bitcast-bfloat-half-mixing.ll

Modified: 
    llvm/lib/IR/Instructions.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index 87874c3abc468..ce0df53d9ffb9 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -3164,7 +3164,7 @@ unsigned CastInst::isEliminableCastPair(
     { 99,99,99, 2, 2,99,99, 8, 2,99,99, 4, 0}, // FPExt          |
     {  1, 0, 0,99,99, 0, 0,99,99,99, 7, 3, 0}, // PtrToInt       |
     { 99,99,99,99,99,99,99,99,99,11,99,15, 0}, // IntToPtr       |
-    {  5, 5, 5, 6, 6, 5, 5, 6, 6,16, 5, 1,14}, // BitCast        |
+    {  5, 5, 5, 0, 0, 5, 5, 0, 0,16, 5, 1,14}, // BitCast        |
     {  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,13,12}, // AddrSpaceCast -+
   };
 
@@ -3213,12 +3213,6 @@ unsigned CastInst::isEliminableCastPair(
       if (SrcTy->isIntegerTy())
         return secondOp;
       return 0;
-    case 6:
-      // No-op cast in first op implies secondOp as long as the SrcTy
-      // is a floating point.
-      if (SrcTy->isFloatingPointTy())
-        return secondOp;
-      return 0;
     case 7: {
       // Disable inttoptr/ptrtoint optimization if enabled.
       if (DisableI2pP2iOpt)

diff  --git a/llvm/test/Transforms/InstCombine/bitcast-bfloat-half-mixing.ll b/llvm/test/Transforms/InstCombine/bitcast-bfloat-half-mixing.ll
new file mode 100644
index 0000000000000..0c4beb223536b
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/bitcast-bfloat-half-mixing.ll
@@ -0,0 +1,87 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -passes=instcombine -S %s | FileCheck %s
+
+define double @F0(bfloat %P0) {
+; CHECK-LABEL: define double @F0(
+; CHECK-SAME: bfloat [[P0:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CONV0:%.*]] = bitcast bfloat [[P0]] to half
+; CHECK-NEXT:    [[TMP0:%.*]] = fpext half [[CONV0]] to double
+; CHECK-NEXT:    ret double [[TMP0]]
+;
+entry:
+  %conv0 = bitcast bfloat %P0 to half
+  %0 = fpext half %conv0 to double
+  ret double %0
+}
+
+define double @F1(half %P1) {
+; CHECK-LABEL: define double @F1(
+; CHECK-SAME: half [[P1:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CONV1:%.*]] = bitcast half [[P1]] to bfloat
+; CHECK-NEXT:    [[TMP0:%.*]] = fpext bfloat [[CONV1]] to double
+; CHECK-NEXT:    ret double [[TMP0]]
+;
+entry:
+  %conv1 = bitcast half %P1 to bfloat
+  %0 = fpext bfloat %conv1 to double
+  ret double %0
+}
+
+define i32 @F2(bfloat %P2) {
+; CHECK-LABEL: define i32 @F2(
+; CHECK-SAME: bfloat [[P2:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CONV2:%.*]] = bitcast bfloat [[P2]] to half
+; CHECK-NEXT:    [[TMP0:%.*]] = fptoui half [[CONV2]] to i32
+; CHECK-NEXT:    ret i32 [[TMP0]]
+;
+entry:
+  %conv2 = bitcast bfloat %P2 to half
+  %0 = fptoui half %conv2 to i32
+  ret i32 %0
+}
+
+define i32 @F3(half %P3) {
+; CHECK-LABEL: define i32 @F3(
+; CHECK-SAME: half [[P3:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CONV3:%.*]] = bitcast half [[P3]] to bfloat
+; CHECK-NEXT:    [[TMP0:%.*]] = fptoui bfloat [[CONV3]] to i32
+; CHECK-NEXT:    ret i32 [[TMP0]]
+;
+entry:
+  %conv3 = bitcast half %P3 to bfloat
+  %0 = fptoui bfloat %conv3 to i32
+  ret i32 %0
+}
+
+define i32 @F4(bfloat %P4) {
+; CHECK-LABEL: define i32 @F4(
+; CHECK-SAME: bfloat [[P4:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CONV4:%.*]] = bitcast bfloat [[P4]] to half
+; CHECK-NEXT:    [[TMP0:%.*]] = fptosi half [[CONV4]] to i32
+; CHECK-NEXT:    ret i32 [[TMP0]]
+;
+entry:
+  %conv4 = bitcast bfloat %P4 to half
+  %0 = fptosi half %conv4 to i32
+  ret i32 %0
+}
+
+define i32 @F5(half %P5) {
+; CHECK-LABEL: define i32 @F5(
+; CHECK-SAME: half [[P5:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CONV5:%.*]] = bitcast half [[P5]] to bfloat
+; CHECK-NEXT:    [[TMP0:%.*]] = fptosi bfloat [[CONV5]] to i32
+; CHECK-NEXT:    ret i32 [[TMP0]]
+;
+entry:
+  %conv5 = bitcast half %P5 to bfloat
+  %0 = fptosi bfloat %conv5 to i32
+  ret i32 %0
+}
+