[llvm] 942cc9a - Revert "[CodeGen] Don't include aliases in RegisterClassInfo::IgnoreCSRForAllocOrder (#80015)"

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2024-01-31T10:25:51Z
New Revision: 942cc9a222343d18339d08516166cfe94445fd13

URL: https://github.com/llvm/llvm-project/commit/942cc9a222343d18339d08516166cfe94445fd13
DIFF: https://github.com/llvm/llvm-project/commit/942cc9a222343d18339d08516166cfe94445fd13.diff

LOG: Revert "[CodeGen] Don't include aliases in RegisterClassInfo::IgnoreCSRForAllocOrder (#80015)"

This reverts commit f8525030004f907cd108e7c18df255a6d3b23124.

It was supposed to speed things up but llvm-compile-time-tracker.com
showed a slight slow down.

Added: 
    

Modified: 
    llvm/lib/CodeGen/RegisterClassInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index 1dd595bc140cb..8869a861de061 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -93,9 +93,11 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
   // Even if CSR list is same, we could have had a 
diff erent allocation order
   // if ignoreCSRForAllocationOrder is evaluated 
diff erently.
   BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
-  for (MCPhysReg I = 1, E = TRI->getNumRegs(); I != E; ++I)
-    CSRHintsForAllocOrder[I] = STI.ignoreCSRForAllocationOrder(mf, I);
-  if (IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
+  for (const MCPhysReg *I = CSR; *I; ++I)
+    for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
+      CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
+  if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
+      IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
     Update = true;
     IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;
   }