[llvm] [LLVM][RISCV][BF16] Support Inline ASM for the bf16 type. (PR #80118)

[Jim Lin via llvm-commits]

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@@ -19343,6 +19345,11 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         unsigned HReg = RISCV::F0_H + RegNo;
         return std::make_pair(HReg, &RISCV::FPR16RegClass);
       }
+      if (Subtarget.hasStdExtZfbfmin() && VT == MVT::bf16) {
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tclin914 wrote:

Look like the same with the one for f16. Could we merge.

https://github.com/llvm/llvm-project/pull/80118