[llvm] f852503 - [CodeGen] Don't include aliases in RegisterClassInfo::IgnoreCSRForAllocOrder (#80015)

via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 31 00:16:09 PST 2024


Author: Jay Foad
Date: 2024-01-31T08:16:06Z
New Revision: f8525030004f907cd108e7c18df255a6d3b23124

URL: https://github.com/llvm/llvm-project/commit/f8525030004f907cd108e7c18df255a6d3b23124
DIFF: https://github.com/llvm/llvm-project/commit/f8525030004f907cd108e7c18df255a6d3b23124.diff

LOG: [CodeGen] Don't include aliases in RegisterClassInfo::IgnoreCSRForAllocOrder (#80015)

Previously we called ignoreCSRForAllocationOrder on every alias of every
CSR which was expensive on targets like AMDGPU which define a very large
number of overlapping register tuples.

On such targets it is simpler and faster to call
ignoreCSRForAllocationOrder once for every physical register.

Differential Revision: https://reviews.llvm.org/D146735

Added: 
    

Modified: 
    llvm/lib/CodeGen/RegisterClassInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index 8869a861de061..1dd595bc140cb 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -93,11 +93,9 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
   // Even if CSR list is same, we could have had a 
diff erent allocation order
   // if ignoreCSRForAllocationOrder is evaluated 
diff erently.
   BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
-  for (const MCPhysReg *I = CSR; *I; ++I)
-    for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
-      CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
-  if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
-      IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
+  for (MCPhysReg I = 1, E = TRI->getNumRegs(); I != E; ++I)
+    CSRHintsForAllocOrder[I] = STI.ignoreCSRForAllocationOrder(mf, I);
+  if (IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
     Update = true;
     IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;
   }


        


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