[llvm] [RISCV][Isel] Remove redundant vmerge for the scalable vwadd(u).wv (PR #80079)

[Luke Lau via llvm-commits]

================
@@ -13795,11 +13798,17 @@ static SDValue combineVWADDWSelect(SDNode *N, SelectionDAG &DAG) {
 
   // False value of MergeOp should be all zeros
   SDValue Z = MergeOp->getOperand(2);
-  if (Z.getOpcode() != ISD::INSERT_SUBVECTOR)
-    return SDValue();
-  if (!ISD::isBuildVectorAllZeros(Z.getOperand(1).getNode()))
-    return SDValue();
-  if (!isNullOrNullSplat(Z.getOperand(0)) && !Z.getOperand(0).isUndef())
+
+  // Fixed-length vector
+  if (MergeOpc == RISCVISD::VMERGE_VL) {
+    if (Z.getOpcode() != ISD::INSERT_SUBVECTOR)
+      return SDValue();
+    if (!isNullOrNullSplat(Z.getOperand(0)) && !Z.getOperand(0).isUndef())
+      return SDValue();
+    Z = Z.getOperand(1);
+  }
----------------
lukel97 wrote:

Thanks! I think we could also probably drop the VMERGE_VL check and make it more generic like this

```suggestion
  if (Z.getOpcode() == ISD::INSERT_SUBVECTOR &&
     (isNullOrNullSplat(Z.getOperand(0)) || Z.getOperand(0).isUndef()))
    Z = Z.getOperand(1);
```

https://github.com/llvm/llvm-project/pull/80079