[llvm] [RISCV][Isel] Remove redundant vmerge for the scalable vwadd(u).wv (PR #80079)

[via llvm-commits]

================
@@ -13795,13 +13798,22 @@ static SDValue combineVWADDWSelect(SDNode *N, SelectionDAG &DAG) {
 
   // False value of MergeOp should be all zeros
   SDValue Z = MergeOp->getOperand(2);
-  if (Z.getOpcode() != ISD::INSERT_SUBVECTOR)
-    return SDValue();
-  if (!ISD::isBuildVectorAllZeros(Z.getOperand(1).getNode()))
-    return SDValue();
-  if (!isNullOrNullSplat(Z.getOperand(0)) && !Z.getOperand(0).isUndef())
+
+  // Scalable vector
+  if (MergeOpc == ISD::VSELECT &&
+      !ISD::isConstantSplatVectorAllZeros(Z.getNode()))
----------------
sun-jacobi wrote:

`ISD::isConstantSplatVectorAllZeros` does not work for the fixed length case. Opcode need to be `ISD::BUILD_VECTOR`.

```cpp
bool ISD::isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly) {
  // Look through a bit convert.
  while (N->getOpcode() == ISD::BITCAST)
    N = N->getOperand(0).getNode();

  if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) {
    APInt SplatVal;
    return isConstantSplatVector(N, SplatVal) && SplatVal.isZero();
  }

  if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
  ...
}
```

https://github.com/llvm/llvm-project/pull/80079