[llvm] [AMDGPU] Insert spill codes for the SGPRs used for EXEC copy (PR #79428)

[Christudasan Devadasan via llvm-commits]

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@@ -1515,11 +1517,15 @@ void SIFrameLowering::determinePrologEpilogSGPRSaves(
       LiveUnits.addReg(UnusedScratchReg);
     } else {
       // Needs spill.
-      assert(!MFI->hasPrologEpilogSGPRSpillEntry(ReservedReg) &&
+      assert(!MFI->hasPrologEpilogSGPRSpillEntry(ReservedRegForExecCopy) &&
              "Re-reserving spill slot for EXEC copy register");
-      getVGPRSpillLaneOrTempRegister(MF, LiveUnits, ReservedReg, RC,
+      getVGPRSpillLaneOrTempRegister(MF, LiveUnits, ReservedRegForExecCopy, RC,
                                      /*IncludeScratchCopy=*/false);
     }
+  } else if (ReservedRegForExecCopy) {
+    // Reset it at this point. There are no whole-wave copies and spills
+    // encountered.
+    MFI->setSGPRForEXECCopy(AMDGPU::NoRegister);
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cdevadas wrote:

Yes. It happens when we have the spills inserted during SILowerSGPRSpills and at that point we ensure there is a reserved register for Exec copy. But vgpr-regalloc didn't insert a liverange spill/copy for the wwm-registers. 

https://github.com/llvm/llvm-project/pull/79428