[llvm] 30b9140 - [RISCV] Minor cleanup to rori MC layer testing. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-01-30T12:24:16-08:00
New Revision: 30b9140c148923e31a6dbcb2202ef3908481bb29

URL: https://github.com/llvm/llvm-project/commit/30b9140c148923e31a6dbcb2202ef3908481bb29
DIFF: https://github.com/llvm/llvm-project/commit/30b9140c148923e31a6dbcb2202ef3908481bb29.diff

LOG: [RISCV] Minor cleanup to rori MC layer testing. NFC

rv32zbb-valid.s tests rv64 and rv32. rv32zbb-only-valid.s only tests rv32.

The rori tests in rv32zbb-only-valid.s produce the same result for rv32 and
rv64 so its better to test them in rv32zbb-valid.s.

Remove a now redundant test case from rv64zbb-valid.s.
Add a missing rori test with imm >= 32 to rv64zbkb-valid.s.

Added: 
    

Modified: 
    llvm/test/MC/RISCV/rv32zbb-only-valid.s
    llvm/test/MC/RISCV/rv32zbb-valid.s
    llvm/test/MC/RISCV/rv64zbb-valid.s
    llvm/test/MC/RISCV/rv64zbkb-valid.s

Removed: 
    


################################################################################
diff  --git a/llvm/test/MC/RISCV/rv32zbb-only-valid.s b/llvm/test/MC/RISCV/rv32zbb-only-valid.s
index 3f95047146019..8cee959ed4275 100644
--- a/llvm/test/MC/RISCV/rv32zbb-only-valid.s
+++ b/llvm/test/MC/RISCV/rv32zbb-only-valid.s
@@ -8,12 +8,6 @@
 # CHECK-ASM-AND-OBJ: zext.h t0, t1
 # CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08]
 zext.h t0, t1
-# CHECK-ASM-AND-OBJ: rori t0, t1, 31
-# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
-rori t0, t1, 31
-# CHECK-ASM-AND-OBJ: rori t0, t1, 0
-# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
-rori t0, t1, 0
 # CHECK-ASM-AND-OBJ: rev8 t0, t1
 # CHECK-ASM: encoding: [0x93,0x52,0x83,0x69]
 rev8 t0, t1

diff  --git a/llvm/test/MC/RISCV/rv32zbb-valid.s b/llvm/test/MC/RISCV/rv32zbb-valid.s
index 2e5b9cce39509..1ed069ed0bdc8 100644
--- a/llvm/test/MC/RISCV/rv32zbb-valid.s
+++ b/llvm/test/MC/RISCV/rv32zbb-valid.s
@@ -4,10 +4,10 @@
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+zbb -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbb < %s \
-# RUN:     | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+zbb --no-print-imm-hex -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbb < %s \
-# RUN:     | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \
+# RUN:     | llvm-objdump --mattr=+zbb --no-print-imm-hex -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # CHECK-ASM-AND-OBJ: clz t0, t1
@@ -55,6 +55,12 @@ rol t0, t1, t2
 # CHECK-ASM-AND-OBJ: ror t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60]
 ror t0, t1, t2
+# CHECK-ASM-AND-OBJ: rori t0, t1, 31
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
+rori t0, t1, 31
+# CHECK-ASM-AND-OBJ: rori t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
+rori t0, t1, 0
 # CHECK-ASM-AND-OBJ: orc.b t0, t1
 # CHECK-ASM: encoding: [0x93,0x52,0x73,0x28]
 orc.b t0, t1

diff  --git a/llvm/test/MC/RISCV/rv64zbb-valid.s b/llvm/test/MC/RISCV/rv64zbb-valid.s
index d2a77f3c65177..6c7327f65dd0a 100644
--- a/llvm/test/MC/RISCV/rv64zbb-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbb-valid.s
@@ -11,9 +11,6 @@ zext.h t0, t1
 # CHECK-ASM-AND-OBJ: rori t0, t1, 63
 # CHECK-ASM: encoding: [0x93,0x52,0xf3,0x63]
 rori t0, t1, 63
-# CHECK-ASM-AND-OBJ: rori t0, t1, 0
-# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
-rori t0, t1, 0
 # CHECK-ASM-AND-OBJ: rev8 t0, t1
 # CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b]
 rev8 t0, t1

diff  --git a/llvm/test/MC/RISCV/rv64zbkb-valid.s b/llvm/test/MC/RISCV/rv64zbkb-valid.s
index b821b79d4b53f..fc0541c86ebed 100644
--- a/llvm/test/MC/RISCV/rv64zbkb-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbkb-valid.s
@@ -8,6 +8,9 @@
 # CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b]
 rev8 t0, t1
 
+# CHECK-ASM-AND-OBJ: rori t0, t1, 63
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x63]
+rori t0, t1, 63
 # CHECK-ASM-AND-OBJ: rorw t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60]
 rorw t0, t1, t2