[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)

[via llvm-commits]

================
@@ -327,6 +327,15 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
 
   /// Get the list of MacroFusion predicates.
   virtual std::vector<MacroFusionPredTy> getMacroFusions() const { return {}; };
+
+  // hasVInstructions is used to determine if an architecture supports
+  // vector instructions in relation to Vector CodeGen. By default, it is
+  // assumed that it will not support Vector Instructions, with architecture
+  // specific overrides providing the information where they are implemented.
+  // This was originally used in RISC-V's Init Undef pass but has been moved to
+  // be a virtual function when the pass was refactored to support multiple
+  // architectures.
+  virtual bool hasVInstructions() const { return false; }
----------------
ostannard wrote:

I don't think this name is right, for two reasons:
* It's referring to the RISC-V "V" extension, which doesn't make sense in target-independent code.
* You'e implemented the ARM version which checks for MVE, but not AdvSIMD. If this implementation is correct, then the name is wrong.

I think it would be more accurate to call it something like `needsInitUndef`.

https://github.com/llvm/llvm-project/pull/77770