[llvm] [AArch64][SME] Allow memory operations lowering to custom SME functions. (PR #79263)

[Sander de Smalen via llvm-commits]

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@@ -76,12 +76,66 @@ SDValue AArch64SelectionDAGInfo::EmitMOPS(AArch64ISD::NodeType SDOpcode,
   }
 }
 
+SDValue AArch64SelectionDAGInfo::EmitSpecializedLibcall(
+    SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
+    SDValue Size, RTLIB::Libcall LC) const {
+  const AArch64Subtarget &STI =
+      DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
+  const AArch64TargetLowering *TLI = STI.getTargetLowering();
+  TargetLowering::ArgListTy Args;
+  TargetLowering::ArgListEntry Entry;
+  SDValue Symbol;
+  Entry.Ty = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
+  Entry.Node = Dst;
+  Args.push_back(Entry);
+  EVT Ty = TLI->getPointerTy(DAG.getDataLayout());
+
+  switch (LC) {
+  case RTLIB::MEMCPY:
+    Symbol = DAG.getExternalSymbol("__arm_sc_memcpy", Ty);
+    Entry.Node = Src;
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sdesmalen-arm wrote:

I'm not a fan of defining `Entry.Node` once above, and then partially re-defining it here for a different purpose. For example, this assumes Entry.Ty is set correctly for the uses here and below.
As another example: it sets `Entry.IsSExt` to `false` when `LC == RTLIB::MEMSET`, which is also used for the `Size` argument. But when `LC != RTLIB::MEMSET`, `Entry.IsSExt` is `true`. That means the Size argument will either be sign-extended or not, depending on the value of `LC`. I'm not sure this is intentional.

https://github.com/llvm/llvm-project/pull/79263