[llvm] 2acf302 - [X86][NFC] X86CompressEVEX.cpp - Simplify code after 0c623b58e39cba7e67a0049dbcac87fdcc0103e1
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 30 04:27:26 PST 2024
Author: Shengchen Kan
Date: 2024-01-30T20:26:54+08:00
New Revision: 2acf302c1bd562a648cc5bcd0bac04433696f5f4
URL: https://github.com/llvm/llvm-project/commit/2acf302c1bd562a648cc5bcd0bac04433696f5f4
DIFF: https://github.com/llvm/llvm-project/commit/2acf302c1bd562a648cc5bcd0bac04433696f5f4.diff
LOG: [X86][NFC] X86CompressEVEX.cpp - Simplify code after 0c623b58e39cba7e67a0049dbcac87fdcc0103e1
Added:
Modified:
llvm/lib/Target/X86/X86CompressEVEX.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp
index e1404eca37fb..b16ee87487ef 100644
--- a/llvm/lib/Target/X86/X86CompressEVEX.cpp
+++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp
@@ -225,24 +225,25 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
//
// For AVX512 cases, EVEX prefix is needed in order to carry this information
// thus preventing the transformation to VEX encoding.
- // MOVBE*rr is special because it has semantic of NDD but not set EVEX_B.
- bool IsMovberr =
- MI.getOpcode() == X86::MOVBE32rr || MI.getOpcode() == X86::MOVBE64rr;
+ unsigned Opc = MI.getOpcode();
bool IsND = X86II::hasNewDataDest(TSFlags);
- if ((TSFlags & X86II::EVEX_B) || IsMovberr)
- if ((!IsND && !IsMovberr) || !isRedundantNewDataDest(MI, ST))
- return false;
+ if (TSFlags & X86II::EVEX_B && !IsND)
+ return false;
+ // MOVBE*rr is special because it has semantic of NDD but not set EVEX_B.
+ bool IsNDLike = IsND || Opc == X86::MOVBE32rr || Opc == X86::MOVBE64rr;
+ if (IsNDLike && !isRedundantNewDataDest(MI, ST))
+ return false;
ArrayRef<X86CompressEVEXTableEntry> Table = ArrayRef(X86CompressEVEXTable);
- unsigned Opc = MI.getOpcode();
+ Opc = MI.getOpcode();
const auto *I = llvm::lower_bound(Table, Opc);
if (I == Table.end() || I->OldOpc != Opc) {
- assert(!IsND && "Missing entry for ND instruction");
+ assert(!IsNDLike && "Missing entry for ND-like instruction");
return false;
}
- if (!IsND && !IsMovberr) {
+ if (!IsNDLike) {
if (usesExtendedRegister(MI) || !checkPredicate(I->NewOpc, &ST) ||
!performCustomAdjustments(MI, I->NewOpc))
return false;
@@ -267,7 +268,7 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
llvm_unreachable("Unknown EVEX compression");
}
MI.setAsmPrinterFlag(AsmComment);
- if (IsND || IsMovberr)
+ if (IsNDLike)
MI.tieOperands(0, 1);
return true;
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