[llvm] [AArch64][SVE2] Generate urshr rounding shift rights (PR #78374)

[Usman Nadeem via llvm-commits]

UsmanNadeem wrote:

- `canLowerSRLToRoundingShiftForVT` returns true if the add has NUW or if the number of bits used in the return value allow us to not care about the overflow (tested by rshrnb).

- `srl(add(X, 1 << (ShiftValue - 1)), ShiftValue)` is transformed to `urshr` or `rshrnb` if the result it truncated.

- `uzp1(rshrnb(uunpklo(X),C), rshrnb(uunpkhi(X), C))` is converted to `urshr(X, C)`, tested by the wide_trunc tests.

https://github.com/llvm/llvm-project/pull/78374