[llvm] [RISCV] Add srmcfg CSR from Ssqosid extension. (PR #79914)

via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 29 15:48:56 PST 2024


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-mc

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

Based on the spec here https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1

Ssqosid extension name will be added in a separate patch.

---
Full diff: https://github.com/llvm/llvm-project/pull/79914.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVSystemOperands.td (+5) 
- (modified) llvm/test/MC/RISCV/supervisor-csr-names.s (+18) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 43475e825b46fb..f046312b1d4284 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -132,6 +132,11 @@ def : SysReg<"sip", 0x144>;
 let DeprecatedName = "sptbr" in
 def : SysReg<"satp", 0x180>;
 
+//===----------------------------------------------------------------------===//
+// Quality-of-Service(QoS) Identifiers (Ssqosid)
+//===----------------------------------------------------------------------===//
+def : SysReg<"srmcfg", 0x181>;
+
 //===----------------------------------------------------------------------===//
 // Debug/Trace Registers
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s
index 84f9edd595d093..127812de4bdc9b 100644
--- a/llvm/test/MC/RISCV/supervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -196,6 +196,24 @@ csrrs t1, satp, zero
 # uimm12
 csrrs t2, 0x180, zero
 
+#########################################
+# Quality-of-Service(QoS) Identifiers
+#########################################
+
+# srmcfg
+# name
+# CHECK-INST: csrrs t1, srmcfg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x18]
+# CHECK-INST-ALIAS: csrr t1, srmcfg
+# uimm12
+# CHECK-INST: csrrs t2, srmcfg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x18]
+# CHECK-INST-ALIAS: csrr t2, srmcfg
+# name
+csrrs t1, srmcfg, zero
+# uimm12
+csrrs t2, 0x181, zero
+
 #########################################
 # Debug/Trace Registers
 #########################################

``````````

</details>


https://github.com/llvm/llvm-project/pull/79914


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