[llvm] [AArch64][SVE2] Generate urshr rounding shift rights (PR #78374)

David Green via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 29 10:24:05 PST 2024


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@@ -10,7 +10,7 @@ define void @add_lshr_rshrnb_b_6(ptr %ptr, ptr %dst, i64 %index){
 ; CHECK-NEXT:    st1b { z0.h }, p0, [x1, x2]
 ; CHECK-NEXT:    ret
   %load = load <vscale x 8 x i16>, ptr %ptr, align 2
-  %1 = add <vscale x 8 x i16> %load, trunc (<vscale x 8 x i32> shufflevector (<vscale x 8 x i32> insertelement (<vscale x 8 x i32> poison, i32 32, i64 0), <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer) to <vscale x 8 x i16>)
+  %1 = add nuw <vscale x 8 x i16> %load, trunc (<vscale x 8 x i32> shufflevector (<vscale x 8 x i32> insertelement (<vscale x 8 x i32> poison, i32 32, i64 0), <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer) to <vscale x 8 x i16>)
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davemgreen wrote:

As far as I understand, correct me if it doesn't sound right, these wouldn't need nuw. Only the lower 8 bits are demanded by the store, so even if the add overflowed it would only shift the overflow '1' by up to 8 bits, so would not end up in the result. Are these changed needed because the urshrnb is now a combine on a urshr?

https://github.com/llvm/llvm-project/pull/78374


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