[llvm] 3ab5dbb - [X86] sext-i1.ll - replace X32 check prefixes with X86
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 29 10:00:48 PST 2024
Author: Simon Pilgrim
Date: 2024-01-29T18:00:36Z
New Revision: 3ab5dbb1995982ab7d106e39a719daaea8bdfeee
URL: https://github.com/llvm/llvm-project/commit/3ab5dbb1995982ab7d106e39a719daaea8bdfeee
DIFF: https://github.com/llvm/llvm-project/commit/3ab5dbb1995982ab7d106e39a719daaea8bdfeee.diff
LOG: [X86] sext-i1.ll - replace X32 check prefixes with X86
We try to only use X32 for gnux32 triple tests.
Added:
Modified:
llvm/test/CodeGen/X86/sext-i1.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/sext-i1.ll b/llvm/test/CodeGen/X86/sext-i1.ll
index 03799af1e70a44..7a906aed1a42e8 100644
--- a/llvm/test/CodeGen/X86/sext-i1.ll
+++ b/llvm/test/CodeGen/X86/sext-i1.ll
@@ -1,17 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i386-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=i386-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=X64
; rdar://7573216
; PR6146
define i32 @t1(i32 %x) nounwind readnone ssp {
-; X32-LABEL: t1:
-; X32: # %bb.0:
-; X32-NEXT: xorl %eax, %eax
-; X32-NEXT: cmpl $1, {{[0-9]+}}(%esp)
-; X32-NEXT: sbbl %eax, %eax
-; X32-NEXT: retl
+; X86-LABEL: t1:
+; X86: # %bb.0:
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: cmpl $1, {{[0-9]+}}(%esp)
+; X86-NEXT: sbbl %eax, %eax
+; X86-NEXT: retl
;
; X64-LABEL: t1:
; X64: # %bb.0:
@@ -25,12 +25,12 @@ define i32 @t1(i32 %x) nounwind readnone ssp {
}
define i32 @t2(i32 %x) nounwind readnone ssp {
-; X32-LABEL: t2:
-; X32: # %bb.0:
-; X32-NEXT: xorl %eax, %eax
-; X32-NEXT: cmpl $1, {{[0-9]+}}(%esp)
-; X32-NEXT: sbbl %eax, %eax
-; X32-NEXT: retl
+; X86-LABEL: t2:
+; X86: # %bb.0:
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: cmpl $1, {{[0-9]+}}(%esp)
+; X86-NEXT: sbbl %eax, %eax
+; X86-NEXT: retl
;
; X64-LABEL: t2:
; X64: # %bb.0:
@@ -44,16 +44,16 @@ define i32 @t2(i32 %x) nounwind readnone ssp {
}
define i32 @t3(i32 %x, i64 %y) nounwind readonly {
-; X32-LABEL: t3:
-; X32: # %bb.0: # %entry
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: xorl %ecx, %ecx
-; X32-NEXT: cmpl $1, {{[0-9]+}}(%esp)
-; X32-NEXT: sbbl %ecx, %ecx
-; X32-NEXT: cmpl %ecx, {{[0-9]+}}(%esp)
-; X32-NEXT: sbbl %ecx, %eax
-; X32-NEXT: xorl %eax, %eax
-; X32-NEXT: retl
+; X86-LABEL: t3:
+; X86: # %bb.0: # %entry
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: cmpl $1, {{[0-9]+}}(%esp)
+; X86-NEXT: sbbl %ecx, %ecx
+; X86-NEXT: cmpl %ecx, {{[0-9]+}}(%esp)
+; X86-NEXT: sbbl %ecx, %eax
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: retl
;
; X64-LABEL: t3:
; X64: # %bb.0: # %entry
@@ -81,14 +81,14 @@ if.end:
}
define i32 @t4(i64 %x) nounwind readnone ssp {
-; X32-LABEL: t4:
-; X32: # %bb.0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT: xorl %eax, %eax
-; X32-NEXT: orl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT: sete %al
-; X32-NEXT: negl %eax
-; X32-NEXT: retl
+; X86-LABEL: t4:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: orl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: sete %al
+; X86-NEXT: negl %eax
+; X86-NEXT: retl
;
; X64-LABEL: t4:
; X64: # %bb.0:
@@ -102,13 +102,13 @@ define i32 @t4(i64 %x) nounwind readnone ssp {
}
define i64 @t5(i32 %x) nounwind readnone ssp {
-; X32-LABEL: t5:
-; X32: # %bb.0:
-; X32-NEXT: xorl %eax, %eax
-; X32-NEXT: cmpl $1, {{[0-9]+}}(%esp)
-; X32-NEXT: sbbl %eax, %eax
-; X32-NEXT: movl %eax, %edx
-; X32-NEXT: retl
+; X86-LABEL: t5:
+; X86: # %bb.0:
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: cmpl $1, {{[0-9]+}}(%esp)
+; X86-NEXT: sbbl %eax, %eax
+; X86-NEXT: movl %eax, %edx
+; X86-NEXT: retl
;
; X64-LABEL: t5:
; X64: # %bb.0:
@@ -124,12 +124,12 @@ define i64 @t5(i32 %x) nounwind readnone ssp {
; sext (xor Bool, -1) --> sub (zext Bool), 1
define i32 @select_0_or_1s(i1 %cond) {
-; X32-LABEL: select_0_or_1s:
-; X32: # %bb.0:
-; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: andl $1, %eax
-; X32-NEXT: decl %eax
-; X32-NEXT: retl
+; X86-LABEL: select_0_or_1s:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: decl %eax
+; X86-NEXT: retl
;
; X64-LABEL: select_0_or_1s:
; X64: # %bb.0:
@@ -145,11 +145,11 @@ define i32 @select_0_or_1s(i1 %cond) {
; sext (xor Bool, -1) --> sub (zext Bool), 1
define i32 @select_0_or_1s_zeroext(i1 zeroext %cond) {
-; X32-LABEL: select_0_or_1s_zeroext:
-; X32: # %bb.0:
-; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: decl %eax
-; X32-NEXT: retl
+; X86-LABEL: select_0_or_1s_zeroext:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: decl %eax
+; X86-NEXT: retl
;
; X64-LABEL: select_0_or_1s_zeroext:
; X64: # %bb.0:
@@ -164,12 +164,12 @@ define i32 @select_0_or_1s_zeroext(i1 zeroext %cond) {
; sext (xor Bool, -1) --> sub (zext Bool), 1
define i32 @select_0_or_1s_signext(i1 signext %cond) {
-; X32-LABEL: select_0_or_1s_signext:
-; X32: # %bb.0:
-; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: andl $1, %eax
-; X32-NEXT: decl %eax
-; X32-NEXT: retl
+; X86-LABEL: select_0_or_1s_signext:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: decl %eax
+; X86-NEXT: retl
;
; X64-LABEL: select_0_or_1s_signext:
; X64: # %bb.0:
@@ -182,11 +182,11 @@ define i32 @select_0_or_1s_signext(i1 signext %cond) {
}
define i32 @zext_decrement_sext(i8 %x) {
-; X32-LABEL: zext_decrement_sext:
-; X32: # %bb.0:
-; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: decl %eax
-; X32-NEXT: retl
+; X86-LABEL: zext_decrement_sext:
+; X86: # %bb.0:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: decl %eax
+; X86-NEXT: retl
;
; X64-LABEL: zext_decrement_sext:
; X64: # %bb.0:
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