[llvm] [RFC] implement convergence control in MIR using SelectionDAG (PR #71785)

[Matt Arsenault via llvm-commits]

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@@ -394,6 +394,16 @@ Register FunctionLoweringInfo::CreateRegs(const Value *V) {
                                       !TLI->requiresUniformRegister(*MF, V));
 }
 
+Register FunctionLoweringInfo::InitializeRegForValue(const Value *V) {
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arsenm wrote:

Why did you move this out of line?

https://github.com/llvm/llvm-project/pull/71785