[llvm] [RFC] implement convergence control in MIR using SelectionDAG (PR #71785)

[Matt Arsenault via llvm-commits]

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@@ -14775,6 +14798,21 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
       AddIMGInit(MI);
     TII->enforceOperandRCAlignment(MI, AMDGPU::OpName::vaddr);
   }
+
+  if (MI.getOpcode() == AMDGPU::CONVERGENCECTRL_GLUE) {
+    MI.getOperand(0).setIsKill(false);
+  }
+
+  if (SDNode *GluedNode = Node->getGluedNode()) {
+    // FIXME: Possibly iterate over multiple glue nodes?
+    GluedNode->dump();
+    if (GluedNode->getOpcode() == ~(unsigned)AMDGPU::CONVERGENCECTRL_GLUE) {
+      Register VReg = getVR(GluedNode->getOperand(0));
+      MachineOperand MO = MachineOperand::CreateReg(VReg, /* isDef = */ false,
+                                                    /* isImp = */ true);
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arsenm wrote:

No space before = to be recognized by clang-format 

https://github.com/llvm/llvm-project/pull/71785