[llvm] [AMDGPU] Fix mul combine for MUL24 (PR #79110)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 29 01:04:31 PST 2024
================
@@ -4254,10 +4254,6 @@ SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
return DAG.getNode(ISD::ADD, DL, VT, MulVal, N0);
}
- // Skip if already mul24.
- if (N->getOpcode() != ISD::MUL)
----------------
arsenm wrote:
Probably should turn this into an assert? Is there definitely nothing else in performMulCombine that can operate on mul24?
https://github.com/llvm/llvm-project/pull/79110
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