[llvm] [RISCV] Add branch+c.mv macrofusion for sifive-p450. (PR #76169)

[Wang Pengcheng via llvm-commits]

================
@@ -112,6 +112,10 @@ def WriteFST16        : SchedWrite;    // Floating point sp store
 def WriteFST32        : SchedWrite;    // Floating point sp store
 def WriteFST64        : SchedWrite;    // Floating point dp store
 
+// CMOV for sifive-p450.
----------------
wangpc-pp wrote:

Thanks, your thought makes sense to me. My concern is that we won't have CMOV in the near future and we need a `UnsupportedCMOV` for almost all new schedule models (except SiFive's), which is already the situation for `UnsupportedSchedSFB`. This is because SFB and this CMOV are only for vendor extensions/features and my thought/strategy is that we should seperate vendor-specific parts from **standard** parts.
Actually, I think there should be a `RISCVInstrInfoSFB.td` which is split out from `RISCVInstrInfo.td`.

https://github.com/llvm/llvm-project/pull/76169