[llvm] [X86] Support EVEX compression from MOVBErr to BSWAP (PR #79775)

[via llvm-commits]

https://github.com/XinWang10 updated https://github.com/llvm/llvm-project/pull/79775

>From a7f4c0c1f1f4025391abfbe9ff8d4a59bbc95bda Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Sun, 28 Jan 2024 18:22:05 -0800
Subject: [PATCH 1/2] [X86] Support encoding compress from movberr to bwap

---
 llvm/lib/Target/X86/X86CompressEVEX.cpp             |  7 +++++--
 llvm/test/CodeGen/X86/apx/compress-evex.mir         | 10 ++++++++++
 llvm/utils/TableGen/X86ManualCompressEVEXTables.def |  2 ++
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp
index a9704e30478d13..7c018f54b7e0a7 100644
--- a/llvm/lib/Target/X86/X86CompressEVEX.cpp
+++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp
@@ -225,8 +225,11 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
   //
   // For AVX512 cases, EVEX prefix is needed in order to carry this information
   // thus preventing the transformation to VEX encoding.
-  bool IsND = X86II::hasNewDataDest(TSFlags);
-  if (TSFlags & X86II::EVEX_B)
+  // MOVBE*rr is special because it has sematic of NDD but not set EVEX_B.
+  bool IsMovberr =
+      MI.getOpcode() == X86::MOVBE32rr || MI.getOpcode() == X86::MOVBE64rr;
+  bool IsND = X86II::hasNewDataDest(TSFlags) || IsMovberr;
+  if (TSFlags & X86II::EVEX_B || IsMovberr)
     if (!IsND || !isRedundantNewDataDest(MI, ST))
       return false;
 
diff --git a/llvm/test/CodeGen/X86/apx/compress-evex.mir b/llvm/test/CodeGen/X86/apx/compress-evex.mir
index 5a3d7ceb10c432..997a8395aa752f 100644
--- a/llvm/test/CodeGen/X86/apx/compress-evex.mir
+++ b/llvm/test/CodeGen/X86/apx/compress-evex.mir
@@ -71,3 +71,13 @@ body:             |
     renamable $rax = XOR64rr_NF_ND killed renamable $rax, killed renamable $r16
     RET64 $rax
 ...
+---
+name:            bswapr_to_movberr
+body:             |
+  bb.0.entry:
+    liveins: $rax
+    ; CHECK: bswapq  %rax                            # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xc8]
+    renamable $rax = MOVBE64rr killed renamable $rax
+    RET64 killed $rax
+
+...
diff --git a/llvm/utils/TableGen/X86ManualCompressEVEXTables.def b/llvm/utils/TableGen/X86ManualCompressEVEXTables.def
index 58ca10e9e10f8d..77cf65be684256 100644
--- a/llvm/utils/TableGen/X86ManualCompressEVEXTables.def
+++ b/llvm/utils/TableGen/X86ManualCompressEVEXTables.def
@@ -328,4 +328,6 @@ ENTRY(VBROADCASTSDZ256rm, VBROADCASTSDYrm)
 ENTRY(VBROADCASTSDZ256rr, VBROADCASTSDYrr)
 ENTRY(VPBROADCASTQZ256rm, VPBROADCASTQYrm)
 ENTRY(VPBROADCASTQZ256rr, VPBROADCASTQYrr)
+ENTRY(MOVBE32rr, BSWAP32r)
+ENTRY(MOVBE64rr, BSWAP64r)
 #undef ENTRY

>From ca9789099de787111ca29e1ae653a5f02af02138 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Sun, 28 Jan 2024 19:41:52 -0800
Subject: [PATCH 2/2] fix typo

---
 llvm/lib/Target/X86/X86CompressEVEX.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp
index 7c018f54b7e0a7..985215bfea1961 100644
--- a/llvm/lib/Target/X86/X86CompressEVEX.cpp
+++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp
@@ -225,7 +225,7 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
   //
   // For AVX512 cases, EVEX prefix is needed in order to carry this information
   // thus preventing the transformation to VEX encoding.
-  // MOVBE*rr is special because it has sematic of NDD but not set EVEX_B.
+  // MOVBE*rr is special because it has semantic of NDD but not set EVEX_B.
   bool IsMovberr =
       MI.getOpcode() == X86::MOVBE32rr || MI.getOpcode() == X86::MOVBE64rr;
   bool IsND = X86II::hasNewDataDest(TSFlags) || IsMovberr;