[llvm] [AMDGPU] Mark PC_ADD_REL_OFFSET rematerializable (PR #79674)

[Yaxun Liu via llvm-commits]

https://github.com/yxsamliu created https://github.com/llvm/llvm-project/pull/79674

Currently machine LICM hoist PC_ADD_REL_OFFSET out of loops, causes register pressure when function calls are deep in loops. This is a main cause of sgpr spill for programs containing large number of function calls in loops.

This patch marks PC_ADD_REL_OFFSET as rematerializable, which eliminates sgpr spills due to function calls in loops. It significantly improves performance of HIP apps which have large number of function calls, e.g., Blender.

>From eebf4110e2ec90f38d279739c5cabc4bbc6ffe13 Mon Sep 17 00:00:00 2001
From: "Yaxun (Sam) Liu" <yaxun.liu at amd.com>
Date: Thu, 25 Jan 2024 23:56:16 -0500
Subject: [PATCH] [AMDGPU] Mark PC_ADD_REL_OFFSET rematerializable

Currently machine LICM hoist PC_ADD_REL_OFFSET out of loops,
causes register pressure when function calls are deep in
loops. This is a main cause of sgpr spill for programs
containing large number of function calls in loops.

This patch marks PC_ADD_REL_OFFSET as rematerializable,
which eliminates sgpr spills due to function calls
in loops. It significantly improves performance of
HIP apps which have large number of function calls,
e.g., Blender.
---
 llvm/lib/Target/AMDGPU/SIInstructions.td | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 788e3162fb37e21..b593b7dbfe08271 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -1036,6 +1036,7 @@ let isConvergent = 1 in {
   defm SI_SPILL_WWM_AV32 : SI_SPILL_VGPR <AV_32, 1>;
 }
 
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def SI_PC_ADD_REL_OFFSET : SPseudoInstSI <
   (outs SReg_64:$dst),
   (ins si_ga:$ptr_lo, si_ga:$ptr_hi),