[llvm] [RISCV] Add branch+c.mv macrofusion for sifive-p450. (PR #76169)

[Michael Maitland via llvm-commits]

================
@@ -112,6 +112,10 @@ def WriteFST16        : SchedWrite;    // Floating point sp store
 def WriteFST32        : SchedWrite;    // Floating point sp store
 def WriteFST64        : SchedWrite;    // Floating point dp store
 
+// CMOV for sifive-p450.
----------------
michaelmaitland wrote:

Why is having a `WriteCMOV` and a `ReadCMOV` intrusive? How are these `Sched<Read|Write>` different than any other `Sched<Read|Write>`? I understand that not every CPU may use the CMOV instructions, but this is the case for CPUs that do not use vector instructions.

It is my understanding that if a CPU does not implement vector instructions, then it doesn't need to specify WriteRes and ReadAdvance for vector instructions, as this is the case in the `RocketModel`. It would be the same thing for CMOV instructions.

I think WriteCMOV and ReadCMOV are minimally invasive. It is my goal to use `InstRW` as little as possible in the SchedModels -- SchedRead and SchedWrite aim to replace InstRW in my opinion.

https://github.com/llvm/llvm-project/pull/76169