[llvm] 59bf605 - Refactor recomputeLiveIns to operate on whole CFG (#79498)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 26 11:25:40 PST 2024
Author: Oskar Wirga
Date: 2024-01-26T11:25:36-08:00
New Revision: 59bf60519fc30d9d36c86abd83093b068f6b1e4b
URL: https://github.com/llvm/llvm-project/commit/59bf60519fc30d9d36c86abd83093b068f6b1e4b
DIFF: https://github.com/llvm/llvm-project/commit/59bf60519fc30d9d36c86abd83093b068f6b1e4b.diff
LOG: Refactor recomputeLiveIns to operate on whole CFG (#79498)
Currently, the way that recomputeLiveIns works is that it will recompute
the livein registers for that MachineBasicBlock but it matters what
order you call recomputeLiveIn which can result in incorrect register
allocations down the line.
This PR fixes that by simply recomputing the liveins for the entire CFG
until convergence is achieved. This makes it harder to introduce subtle
bugs which alter liveness.
Added:
Modified:
llvm/include/llvm/CodeGen/LivePhysRegs.h
llvm/include/llvm/CodeGen/MachineBasicBlock.h
llvm/lib/CodeGen/BranchFolding.cpp
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
llvm/lib/Target/X86/X86FrameLowering.cpp
llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
llvm/test/CodeGen/SystemZ/branch-folder-hoist-livein.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/LivePhysRegs.h b/llvm/include/llvm/CodeGen/LivePhysRegs.h
index 76bb34d270a26d..1e0ee9eb9eb320 100644
--- a/llvm/include/llvm/CodeGen/LivePhysRegs.h
+++ b/llvm/include/llvm/CodeGen/LivePhysRegs.h
@@ -31,6 +31,7 @@
#include "llvm/ADT/SparseSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegister.h"
#include "llvm/MC/MCRegisterInfo.h"
@@ -193,11 +194,31 @@ void addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs);
void computeAndAddLiveIns(LivePhysRegs &LiveRegs,
MachineBasicBlock &MBB);
-/// Convenience function for recomputing live-in's for \p MBB.
-static inline void recomputeLiveIns(MachineBasicBlock &MBB) {
+/// Function to update the live-in's for a basic block and return whether any
+/// changes were made.
+static inline bool updateBlockLiveInfo(MachineBasicBlock &MBB) {
LivePhysRegs LPR;
+ auto oldLiveIns = MBB.getLiveIns();
+
MBB.clearLiveIns();
computeAndAddLiveIns(LPR, MBB);
+ MBB.sortUniqueLiveIns();
+
+ auto newLiveIns = MBB.getLiveIns();
+ return oldLiveIns != newLiveIns;
+}
+
+/// Convenience function for recomputing live-in's for the entire CFG until
+/// convergence is reached.
+static inline void recomputeLiveIns(MachineFunction &MF) {
+ bool anyChanged;
+ do {
+ anyChanged = false;
+ for (auto MFI = MF.rbegin(), MFE = MF.rend(); MFI != MFE; ++MFI) {
+ MachineBasicBlock &MBB = *MFI;
+ anyChanged |= updateBlockLiveInfo(MBB);
+ }
+ } while (anyChanged);
}
} // end namespace llvm
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index c84fd281c6a549..dc2035fa598c46 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -111,6 +111,10 @@ class MachineBasicBlock
RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
: PhysReg(PhysReg), LaneMask(LaneMask) {}
+
+ bool operator==(const RegisterMaskPair &other) const {
+ return PhysReg == other.PhysReg && LaneMask == other.LaneMask;
+ }
};
private:
@@ -473,6 +477,8 @@ class MachineBasicBlock
/// Remove entry from the livein set and return iterator to the next.
livein_iterator removeLiveIn(livein_iterator I);
+ std::vector<RegisterMaskPair> getLiveIns() const { return LiveIns; }
+
class liveout_iterator {
public:
using iterator_category = std::input_iterator_tag;
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp
index a9f78358e57b92..9075fa436da58c 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -2048,8 +2048,7 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) {
FBB->erase(FBB->begin(), FIB);
if (UpdateLiveIns) {
- recomputeLiveIns(*TBB);
- recomputeLiveIns(*FBB);
+ recomputeLiveIns(*MBB->getParent());
}
++NumHoist;
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index cffd414221c30c..785f563faf4bb1 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -4339,8 +4339,7 @@ AArch64FrameLowering::inlineStackProbeLoopExactMultiple(
ExitMBB->transferSuccessorsAndUpdatePHIs(&MBB);
MBB.addSuccessor(LoopMBB);
// Update liveins.
- recomputeLiveIns(*LoopMBB);
- recomputeLiveIns(*ExitMBB);
+ recomputeLiveIns(MF);
return ExitMBB->begin();
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 2e8d8c63d6bec2..72722aa95b846e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -9597,9 +9597,7 @@ AArch64InstrInfo::probedStackAlloc(MachineBasicBlock::iterator MBBI,
// Update liveins.
if (MF.getRegInfo().reservedRegsFrozen()) {
- recomputeLiveIns(*LoopTestMBB);
- recomputeLiveIns(*LoopBodyMBB);
- recomputeLiveIns(*ExitMBB);
+ recomputeLiveIns(MF);
}
return ExitMBB->begin();
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 5c1c7046fdbff0..e199a21da500a1 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -1806,12 +1806,7 @@ void ARMLowOverheadLoops::Expand(LowOverheadLoop &LoLoop) {
PostOrderLoopTraversal DFS(LoLoop.ML, *MLI);
DFS.ProcessLoop();
const SmallVectorImpl<MachineBasicBlock*> &PostOrder = DFS.getOrder();
- for (auto *MBB : PostOrder) {
- recomputeLiveIns(*MBB);
- // FIXME: For some reason, the live-in print order is non-deterministic for
- // our tests and I can't out why... So just sort them.
- MBB->sortUniqueLiveIns();
- }
+ recomputeLiveIns(*LoLoop.MF);
for (auto *MBB : reverse(PostOrder))
recomputeLivenessFlags(*MBB);
diff --git a/llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp
index aee57a5075ff71..c170bafe9b184c 100644
--- a/llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp
@@ -208,8 +208,7 @@ bool PPCExpandAtomicPseudo::expandAtomicRMW128(
.addMBB(LoopMBB);
CurrentMBB->addSuccessor(LoopMBB);
CurrentMBB->addSuccessor(ExitMBB);
- recomputeLiveIns(*LoopMBB);
- recomputeLiveIns(*ExitMBB);
+ recomputeLiveIns(*MF);
NMBBI = MBB.end();
MI.eraseFromParent();
return true;
@@ -286,9 +285,7 @@ bool PPCExpandAtomicPseudo::expandAtomicCmpSwap128(
CurrentMBB->addSuccessor(LoopCmpMBB);
CurrentMBB->addSuccessor(ExitMBB);
- recomputeLiveIns(*LoopCmpMBB);
- recomputeLiveIns(*CmpSuccMBB);
- recomputeLiveIns(*ExitMBB);
+ recomputeLiveIns(*MF);
NMBBI = MBB.end();
MI.eraseFromParent();
return true;
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index 245e78641ed654..f67658302958c3 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -1441,8 +1441,7 @@ void PPCFrameLowering::inlineStackProbe(MachineFunction &MF,
ProbeLoopBodyMBB->addSuccessor(ProbeLoopBodyMBB);
}
// Update liveins.
- recomputeLiveIns(*ProbeLoopBodyMBB);
- recomputeLiveIns(*ProbeExitMBB);
+ recomputeLiveIns(MF);
return ProbeExitMBB;
};
// For case HasBP && MaxAlign > 1, we have to realign the SP by performing
@@ -1534,8 +1533,7 @@ void PPCFrameLowering::inlineStackProbe(MachineFunction &MF,
buildDefCFAReg(*ExitMBB, ExitMBB->begin(), SPReg);
}
// Update liveins.
- recomputeLiveIns(*LoopMBB);
- recomputeLiveIns(*ExitMBB);
+ recomputeLiveIns(MF);
}
}
++NumPrologProbed;
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index db19c8881c685a..965688dec69b25 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -840,8 +840,7 @@ void SystemZELFFrameLowering::inlineStackProbe(
StackAllocMI->eraseFromParent();
if (DoneMBB != nullptr) {
// Compute the live-in lists for the new blocks.
- recomputeLiveIns(*DoneMBB);
- recomputeLiveIns(*LoopMBB);
+ recomputeLiveIns(MF);
}
}
@@ -1439,8 +1438,7 @@ void SystemZXPLINKFrameLowering::inlineStackProbe(
StackAllocMI->eraseFromParent();
// Compute the live-in lists for the new blocks.
- recomputeLiveIns(*NextMBB);
- recomputeLiveIns(*StackExtMBB);
+ recomputeLiveIns(MF);
}
bool SystemZXPLINKFrameLowering::hasFP(const MachineFunction &MF) const {
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
index c0d358ead2787b..4aa27be0791314 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -885,8 +885,7 @@ void X86FrameLowering::emitStackProbeInlineGenericLoop(
}
// Update Live In information
- recomputeLiveIns(*testMBB);
- recomputeLiveIns(*tailMBB);
+ recomputeLiveIns(MF);
}
void X86FrameLowering::emitStackProbeInlineWindowsCoreCLR64(
@@ -1378,10 +1377,7 @@ void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
footMBB->addSuccessor(&MBB);
}
- recomputeLiveIns(*headMBB);
- recomputeLiveIns(*bodyMBB);
- recomputeLiveIns(*footMBB);
- recomputeLiveIns(MBB);
+ recomputeLiveIns(MF);
}
} else {
MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
diff --git a/llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir b/llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
index 6c8ec7e4c4fa92..8d7fab4cc39c66 100644
--- a/llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
+++ b/llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
@@ -82,7 +82,7 @@ body: |
; CHECK-LABEL: name: f
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.3(0x80000000)
- ; CHECK-NEXT: liveins: $lr, $fp
+ ; CHECK-NEXT: liveins: $fp, $lr
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: early-clobber $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2 :: (store (s64) into %stack.2), (store (s64) into %stack.1)
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
diff --git a/llvm/test/CodeGen/SystemZ/branch-folder-hoist-livein.mir b/llvm/test/CodeGen/SystemZ/branch-folder-hoist-livein.mir
index 5e100b88ead300..82e3bae97ec0c4 100644
--- a/llvm/test/CodeGen/SystemZ/branch-folder-hoist-livein.mir
+++ b/llvm/test/CodeGen/SystemZ/branch-folder-hoist-livein.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -verify-machineinstrs -O1 -mtriple=s390x-ibm-linux -o - %s -run-pass=branch-folder | FileCheck %s
--- |
target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"
@@ -15,6 +16,30 @@
name: f1
tracksRegLiveness: true
body: |
+ ; CHECK-LABEL: name: f1
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x7fffffff), %bb.1(0x00000001)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r1d = LGRL @b :: (load (s32) from got, align 8)
+ ; CHECK-NEXT: renamable $r1l = LH killed renamable $r1d, 0, $noreg, implicit-def $r1d :: (dereferenceable load (s8) from @b)
+ ; CHECK-NEXT: renamable $r2l = LHI 0
+ ; CHECK-NEXT: renamable $r3d = LGRL @d :: (load (s32) from got, align 8)
+ ; CHECK-NEXT: renamable $r4d = LLILL 0, implicit-def $r4q
+ ; CHECK-NEXT: renamable $r4d = COPY killed renamable $r4d, implicit killed $r4q
+ ; CHECK-NEXT: CHI killed renamable $r2l, 0, implicit-def $cc
+ ; CHECK-NEXT: BRC 14, 6, %bb.2, implicit killed $cc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors:
+ ; CHECK-NEXT: liveins: $r3d, $r4d, $r1l
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STH renamable $r1l, killed renamable $r3d, 0, $noreg, implicit killed $r4d :: (store (s8) into @d)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: liveins: $r3d, $r4d, $r1l
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STH renamable $r1l, killed renamable $r3d, 0, $noreg, implicit killed $r4d :: (store (s8) into @d)
+ ; CHECK-NEXT: Return
bb.0:
successors: %bb.2(0x7fffffff), %bb.1(0x00000001)
liveins:
@@ -44,14 +69,3 @@ body: |
Return
...
-
-# CHECK: renamable $r4d = COPY killed renamable $r4d, implicit killed $r4q
-# CHECK-NEXT: CHI killed renamable $r2l, 0, implicit-def $cc
-# CHECK-NEXT: BRC 14, 6, %bb.2, implicit killed $cc
-# CHECK-NEXT: {{^ $}}
-# CHECK-NEXT: bb.1:
-# CHECK-NEXT: successors:
-# CHECK-NEXT: liveins: $r1l, $r3d, $r4d
-
-# CHECK: bb.2:
-# CHECK-NEXT: liveins: $r1l, $r3d, $r4d
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
index dabebf4aeb77a8..d9d3fd571ab8de 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
@@ -200,96 +200,108 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: arm_biquad_cascade_df1_q31
; CHECK: bb.0.bb:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
- ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
- ; CHECK: $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 76
- ; CHECK: $r6, $r5 = t2LDRDi8 $r0, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i7), (load (s32) from %ir.i10)
- ; CHECK: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
- ; CHECK: $r3, $r7 = t2LDRDi8 killed $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i), (load (s32) from %ir.i5)
- ; CHECK: renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r8 :: (store (s32) into %stack.9), (store (s32) into %stack.8), (store (s32) into %stack.7)
- ; CHECK: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.9)
- ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
- ; CHECK: bb.1.bb74 (align 4):
- ; CHECK: successors: %bb.6(0x04000000), %bb.2(0x7c000000)
- ; CHECK: liveins: $r0, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12, $r2
- ; CHECK: renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 20, 14 /* CC::al */, $noreg
- ; CHECK: t2STRDi8 killed $r9, killed $r4, $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i14), (store (s32) into %ir.i81)
- ; CHECK: t2STRDi8 killed $r6, killed $r0, $r3, 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i84), (store (s32) into %ir.i88)
- ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r5, $cpsr = tSUBi8 killed renamable $r5, 1, 14 /* CC::al */, $noreg
- ; CHECK: $r1 = tMOVr $r12, 14 /* CC::al */, $noreg
- ; CHECK: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.2.bb12:
- ; CHECK: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $r1, $r2, $r3, $r5, $r7, $r8, $r12
- ; CHECK: $r9, $r4 = t2LDRDi8 $r3, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i14), (load (s32) from %ir.i20)
- ; CHECK: $r6, $r0 = t2LDRDi8 $r3, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i22), (load (s32) from %ir.i24)
- ; CHECK: dead $lr = t2SUBri renamable $r8, 0, 14 /* CC::al */, $noreg, def $cpsr
- ; CHECK: tBcc %bb.1, 0 /* CC::eq */, killed $cpsr
- ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
- ; CHECK: bb.3.bb27:
- ; CHECK: successors: %bb.4(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12
- ; CHECK: t2STRDi8 killed $r3, killed $r5, $sp, 12, 14 /* CC::al */, $noreg :: (store (s32) into %stack.6), (store (s32) into %stack.5)
- ; CHECK: renamable $r3 = tLDRi renamable $r7, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i13)
- ; CHECK: tSTRspi killed renamable $r3, $sp, 9, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
- ; CHECK: renamable $r3 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i34)
- ; CHECK: tSTRspi killed renamable $r3, $sp, 8, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1)
- ; CHECK: renamable $r3 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i32)
- ; CHECK: tSTRspi killed renamable $r3, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2)
- ; CHECK: renamable $r3 = tLDRi renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i30)
- ; CHECK: t2STRDi8 $r7, killed $r3, $sp, 20, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4), (store (s32) into %stack.3)
- ; CHECK: renamable $r10 = t2LDRi12 killed renamable $r7, 16, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i28)
- ; CHECK: bb.4.bb37 (align 4):
- ; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r4, $r6, $r8, $r9, $r10, $r12
- ; CHECK: $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1)
- ; CHECK: renamable $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2)
- ; CHECK: renamable $r6, renamable $r11 = t2SMULL $r9, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r4, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load (s32) from %stack.3)
- ; CHECK: $r5 = tMOVr killed $r9, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i38)
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r0, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r0 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
- ; CHECK: $lr = tMOVr $r8, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r0, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: early-clobber renamable $r12 = t2STR_POST renamable $r6, killed renamable $r12, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i39)
- ; CHECK: dead renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
- ; CHECK: renamable $r8 = t2SUBri killed renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = tMOVr $r7, 14 /* CC::al */, $noreg
- ; CHECK: $r4 = tMOVr $r5, 14 /* CC::al */, $noreg
- ; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
- ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
- ; CHECK: bb.5.bb72:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $r2, $r5, $r6, $r7, $r9
- ; CHECK: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg
- ; CHECK: $r7 = tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
- ; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg
- ; CHECK: $r12, $r8 = t2LDRDi8 $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.8), (load (s32) from %stack.7)
- ; CHECK: tLDMIA killed $r7, 14 /* CC::al */, $noreg, def $r3, def $r5, def $r7 :: (load (s32) from %stack.6), (load (s32) from %stack.5), (load (s32) from %stack.4)
- ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
- ; CHECK: bb.6.bb91:
- ; CHECK: $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg
- ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36
+ ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 76
+ ; CHECK-NEXT: $r6, $r5 = t2LDRDi8 $r0, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i7), (load (s32) from %ir.i10)
+ ; CHECK-NEXT: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r3, $r7 = t2LDRDi8 killed $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i), (load (s32) from %ir.i5)
+ ; CHECK-NEXT: renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r8 :: (store (s32) into %stack.9), (store (s32) into %stack.8), (store (s32) into %stack.7)
+ ; CHECK-NEXT: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.9)
+ ; CHECK-NEXT: tB %bb.2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.bb74 (align 4):
+ ; CHECK-NEXT: successors: %bb.6(0x04000000), %bb.2(0x7c000000)
+ ; CHECK-NEXT: liveins: $r0, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 20, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRDi8 killed $r9, killed $r4, $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i14), (store (s32) into %ir.i81)
+ ; CHECK-NEXT: t2STRDi8 killed $r6, killed $r0, $r3, 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i84), (store (s32) into %ir.i88)
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r5, $cpsr = tSUBi8 killed renamable $r5, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r1 = tMOVr $r12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.bb12:
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $r1, $r2, $r3, $r5, $r7, $r8, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r9, $r4 = t2LDRDi8 $r3, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i14), (load (s32) from %ir.i20)
+ ; CHECK-NEXT: $r6, $r0 = t2LDRDi8 $r3, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i22), (load (s32) from %ir.i24)
+ ; CHECK-NEXT: dead $lr = t2SUBri renamable $r8, 0, 14 /* CC::al */, $noreg, def $cpsr
+ ; CHECK-NEXT: tBcc %bb.1, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: tB %bb.3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.bb27:
+ ; CHECK-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: t2STRDi8 killed $r3, killed $r5, $sp, 12, 14 /* CC::al */, $noreg :: (store (s32) into %stack.6), (store (s32) into %stack.5)
+ ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i13)
+ ; CHECK-NEXT: tSTRspi killed renamable $r3, $sp, 9, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
+ ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i34)
+ ; CHECK-NEXT: tSTRspi killed renamable $r3, $sp, 8, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1)
+ ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i32)
+ ; CHECK-NEXT: tSTRspi killed renamable $r3, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2)
+ ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i30)
+ ; CHECK-NEXT: t2STRDi8 $r7, killed $r3, $sp, 20, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4), (store (s32) into %stack.3)
+ ; CHECK-NEXT: renamable $r10 = t2LDRi12 killed renamable $r7, 16, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i28)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.bb37 (align 4):
+ ; CHECK-NEXT: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r4, $r6, $r8, $r9, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1)
+ ; CHECK-NEXT: renamable $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2)
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMULL $r9, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r4, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load (s32) from %stack.3)
+ ; CHECK-NEXT: $r5 = tMOVr killed $r9, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i38)
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r0, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r0 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
+ ; CHECK-NEXT: $lr = tMOVr $r8, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r0, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: early-clobber renamable $r12 = t2STR_POST renamable $r6, killed renamable $r12, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i39)
+ ; CHECK-NEXT: dead renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
+ ; CHECK-NEXT: renamable $r8 = t2SUBri killed renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = tMOVr $r7, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r4 = tMOVr $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: tB %bb.5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.bb72:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $r2, $r5, $r6, $r7, $r9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r7 = tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r12, $r8 = t2LDRDi8 $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.8), (load (s32) from %stack.7)
+ ; CHECK-NEXT: tLDMIA killed $r7, 14 /* CC::al */, $noreg, def $r3, def $r5, def $r7 :: (load (s32) from %stack.6), (load (s32) from %stack.5), (load (s32) from %stack.4)
+ ; CHECK-NEXT: tB %bb.1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb91:
+ ; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
bb.0.bb:
successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
index 10574ba7320e6d..38c6361eca0225 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
@@ -3,7 +3,6 @@
--- |
%struct.arm_biquad_casd_df1_inst_q31 = type { i32*, i32*, i32, i32 }
- ; Function Attrs: optsize
define hidden void @arm_biquad_cascade_df1_q31(%struct.arm_biquad_casd_df1_inst_q31* nocapture readonly %arg, i32* nocapture readonly %arg1, i32* nocapture %arg2, i32 %arg3) #0 {
bb:
%i = bitcast %struct.arm_biquad_casd_df1_inst_q31* %arg to i32**
@@ -198,83 +197,95 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: arm_biquad_cascade_df1_q31
; CHECK: bb.0.bb:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
- ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
- ; CHECK: $sp = frame-setup tSUBspi $sp, 8, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 68
- ; CHECK: $r6, $r4 = t2LDRDi8 $r0, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i7), (load (s32) from %ir.i10)
- ; CHECK: $r7, $r5 = t2LDRDi8 killed $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i), (load (s32) from %ir.i5)
- ; CHECK: renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r3 :: (store (s32) into %stack.7), (store (s32) into %stack.6), (store (s32) into %stack.5)
- ; CHECK: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.7)
- ; CHECK: bb.1.bb12 (align 4):
- ; CHECK: successors: %bb.2(0x40000000), %bb.5(0x40000000)
- ; CHECK: liveins: $r1, $r2, $r3, $r4, $r5, $r7, $r12
- ; CHECK: $r10, $r0 = t2LDRDi8 $r7, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i14), (load (s32) from %ir.i20)
- ; CHECK: $r6, $r8 = t2LDRDi8 $r7, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i22), (load (s32) from %ir.i24)
- ; CHECK: $lr = t2WLS renamable $r3, %bb.5
- ; CHECK: bb.2.bb27:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r6, $r7, $r8, $r10, $r12
- ; CHECK: renamable $r3 = tLDRi renamable $r5, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i13)
- ; CHECK: t2STRDi8 killed $r7, killed $r4, $sp, 12, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4), (store (s32) into %stack.3)
- ; CHECK: tSTRspi killed renamable $r3, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
- ; CHECK: renamable $r3 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i34)
- ; CHECK: renamable $r4 = tLDRi renamable $r5, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i28)
- ; CHECK: tSTRspi killed renamable $r3, $sp, 6, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1)
- ; CHECK: $r9, $r3 = t2LDRDi8 $r5, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i32), (load (s32) from %ir.i30)
- ; CHECK: tSTRspi killed renamable $r5, $sp, 5, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2)
- ; CHECK: bb.3.bb37 (align 4):
- ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r8, $r9, $r10, $r12
- ; CHECK: $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1)
- ; CHECK: $r5 = tMOVr $r10, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6, renamable $r11 = t2SMULL killed $r10, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r0, renamable $r9, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r10, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i38)
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL renamable $r7, renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r0 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r8, renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL renamable $r10, killed renamable $r0, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: early-clobber renamable $r12 = t2STR_POST renamable $r6, killed renamable $r12, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i39)
- ; CHECK: $r8 = tMOVr $r7, 14 /* CC::al */, $noreg
- ; CHECK: $r0 = tMOVr $r5, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3
- ; CHECK: bb.4.bb72:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $r2, $r5, $r6, $r7, $r10
- ; CHECK: $r0 = tMOVr killed $r5, 14 /* CC::al */, $noreg
- ; CHECK: $r8 = tMOVr killed $r7, 14 /* CC::al */, $noreg
- ; CHECK: $r12, $r3 = t2LDRDi8 $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.6), (load (s32) from %stack.5)
- ; CHECK: renamable $r5 = tLDRspi $sp, 5, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2)
- ; CHECK: $r7, $r4 = t2LDRDi8 $sp, 12, 14 /* CC::al */, $noreg :: (load (s32) from %stack.4), (load (s32) from %stack.3)
- ; CHECK: bb.5.bb74:
- ; CHECK: successors: %bb.6(0x04000000), %bb.1(0x7c000000)
- ; CHECK: liveins: $r0, $r3, $r4, $r5, $r6, $r7, $r8, $r10, $r12, $r2
- ; CHECK: renamable $r5, dead $cpsr = nuw tADDi8 killed renamable $r5, 20, 14 /* CC::al */, $noreg
- ; CHECK: t2STRDi8 killed $r10, killed $r0, $r7, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i14), (store (s32) into %ir.i81)
- ; CHECK: t2STRDi8 killed $r6, killed $r8, $r7, 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i84), (store (s32) into %ir.i88)
- ; CHECK: renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 16, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4, $cpsr = tSUBi8 killed renamable $r4, 1, 14 /* CC::al */, $noreg
- ; CHECK: $r1 = tMOVr $r12, 14 /* CC::al */, $noreg
- ; CHECK: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
- ; CHECK: bb.6.bb91:
- ; CHECK: $sp = frame-destroy tADDspi $sp, 8, 14 /* CC::al */, $noreg
- ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36
+ ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 8, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 68
+ ; CHECK-NEXT: $r6, $r4 = t2LDRDi8 $r0, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i7), (load (s32) from %ir.i10)
+ ; CHECK-NEXT: $r7, $r5 = t2LDRDi8 killed $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i), (load (s32) from %ir.i5)
+ ; CHECK-NEXT: renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r3 :: (store (s32) into %stack.7), (store (s32) into %stack.6), (store (s32) into %stack.5)
+ ; CHECK-NEXT: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.7)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.bb12 (align 4):
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.5(0x40000000)
+ ; CHECK-NEXT: liveins: $r1, $r2, $r3, $r4, $r5, $r7, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r10, $r0 = t2LDRDi8 $r7, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i14), (load (s32) from %ir.i20)
+ ; CHECK-NEXT: $r6, $r8 = t2LDRDi8 $r7, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i22), (load (s32) from %ir.i24)
+ ; CHECK-NEXT: $lr = t2WLS renamable $r3, %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.bb27:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r6, $r7, $r8, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r5, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i13)
+ ; CHECK-NEXT: t2STRDi8 killed $r7, killed $r4, $sp, 12, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4), (store (s32) into %stack.3)
+ ; CHECK-NEXT: tSTRspi killed renamable $r3, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
+ ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i34)
+ ; CHECK-NEXT: renamable $r4 = tLDRi renamable $r5, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i28)
+ ; CHECK-NEXT: tSTRspi killed renamable $r3, $sp, 6, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1)
+ ; CHECK-NEXT: $r9, $r3 = t2LDRDi8 $r5, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i32), (load (s32) from %ir.i30)
+ ; CHECK-NEXT: tSTRspi killed renamable $r5, $sp, 5, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.bb37 (align 4):
+ ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r8, $r9, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1)
+ ; CHECK-NEXT: $r5 = tMOVr $r10, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMULL killed $r10, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r0, renamable $r9, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r10, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i38)
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL renamable $r7, renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r0 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r8, renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL renamable $r10, killed renamable $r0, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: early-clobber renamable $r12 = t2STR_POST renamable $r6, killed renamable $r12, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i39)
+ ; CHECK-NEXT: $r8 = tMOVr $r7, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r0 = tMOVr $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.bb72:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $r2, $r5, $r6, $r7, $r10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r0 = tMOVr killed $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r8 = tMOVr killed $r7, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r12, $r3 = t2LDRDi8 $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.6), (load (s32) from %stack.5)
+ ; CHECK-NEXT: renamable $r5 = tLDRspi $sp, 5, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2)
+ ; CHECK-NEXT: $r7, $r4 = t2LDRDi8 $sp, 12, 14 /* CC::al */, $noreg :: (load (s32) from %stack.4), (load (s32) from %stack.3)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.bb74:
+ ; CHECK-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)
+ ; CHECK-NEXT: liveins: $r0, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = nuw tADDi8 killed renamable $r5, 20, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRDi8 killed $r10, killed $r0, $r7, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i14), (store (s32) into %ir.i81)
+ ; CHECK-NEXT: t2STRDi8 killed $r6, killed $r8, $r7, 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i84), (store (s32) into %ir.i88)
+ ; CHECK-NEXT: renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4, $cpsr = tSUBi8 killed renamable $r4, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r1 = tMOVr $r12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb91:
+ ; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 8, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
bb.0.bb:
successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
index 62a266e3468b3d..e0a7b127123701 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
@@ -4,7 +4,6 @@
--- |
%struct.arm_biquad_casd_df1_inst_q31 = type { i32*, i32*, i32, i32 }
- ; Function Attrs: optsize
define hidden void @arm_biquad_cascade_df1_q31(%struct.arm_biquad_casd_df1_inst_q31* nocapture readonly %arg, i32* nocapture readonly %arg1, i32* nocapture %arg2, i32 %arg3) #0 {
bb:
%i = bitcast %struct.arm_biquad_casd_df1_inst_q31* %arg to i32**
@@ -116,10 +115,8 @@
ret void
}
- ; Function Attrs: noduplicate nounwind
declare i1 @llvm.test.set.loop.iterations.i32(i32) #1
- ; Function Attrs: noduplicate nounwind
declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #1
attributes #0 = { optsize "target-cpu"="cortex-m55" }
@@ -208,90 +205,102 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: arm_biquad_cascade_df1_q31
; CHECK: bb.0.bb:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
- ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
- ; CHECK: $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 76
- ; CHECK: $r6, $r5 = t2LDRDi8 $r0, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i7), (load (s32) from %ir.i10)
- ; CHECK: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
- ; CHECK: $r3, $r7 = t2LDRDi8 killed $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i), (load (s32) from %ir.i5)
- ; CHECK: renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r8 :: (store (s32) into %stack.9), (store (s32) into %stack.8), (store (s32) into %stack.7)
- ; CHECK: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.9)
- ; CHECK: bb.1.bb12 (align 4):
- ; CHECK: successors: %bb.2(0x40000000), %bb.5(0x40000000)
- ; CHECK: liveins: $r1, $r2, $r3, $r5, $r7, $r8, $r12
- ; CHECK: $r9, $r4 = t2LDRDi8 $r3, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i14), (load (s32) from %ir.i20)
- ; CHECK: $r6, $r0 = t2LDRDi8 $r3, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i22), (load (s32) from %ir.i24)
- ; CHECK: dead $lr = t2WLS renamable $r8, %bb.5
- ; CHECK: bb.2.bb27:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12
- ; CHECK: t2STRDi8 killed $r3, killed $r5, $sp, 12, 14 /* CC::al */, $noreg :: (store (s32) into %stack.6), (store (s32) into %stack.5)
- ; CHECK: renamable $r3 = tLDRi renamable $r7, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i13)
- ; CHECK: tSTRspi killed renamable $r3, $sp, 9, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
- ; CHECK: renamable $r3 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i34)
- ; CHECK: tSTRspi killed renamable $r3, $sp, 8, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1)
- ; CHECK: renamable $r3 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i32)
- ; CHECK: tSTRspi killed renamable $r3, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2)
- ; CHECK: renamable $r3 = tLDRi renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i30)
- ; CHECK: t2STRDi8 $r7, killed $r3, $sp, 20, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4), (store (s32) into %stack.3)
- ; CHECK: renamable $r10 = t2LDRi12 killed renamable $r7, 16, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i28)
- ; CHECK: bb.3.bb37 (align 4):
- ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r4, $r6, $r8, $r9, $r10, $r12
- ; CHECK: $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1)
- ; CHECK: renamable $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2)
- ; CHECK: renamable $r6, renamable $r11 = t2SMULL $r9, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r4, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load (s32) from %stack.3)
- ; CHECK: $r5 = tMOVr killed $r9, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i38)
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r0, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r0 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
- ; CHECK: $lr = tMOVr $r8, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r0, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: early-clobber renamable $r12 = t2STR_POST renamable $r6, killed renamable $r12, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i39)
- ; CHECK: renamable $r8 = t2SUBri killed renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = tMOVr $r7, 14 /* CC::al */, $noreg
- ; CHECK: $r4 = tMOVr $r5, 14 /* CC::al */, $noreg
- ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.3
- ; CHECK: bb.4.bb72:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $r2, $r5, $r6, $r7, $r9
- ; CHECK: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg
- ; CHECK: $r7 = tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
- ; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg
- ; CHECK: $r12, $r8 = t2LDRDi8 $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.8), (load (s32) from %stack.7)
- ; CHECK: tLDMIA killed $r7, 14 /* CC::al */, $noreg, def $r3, def $r5, def $r7 :: (load (s32) from %stack.6), (load (s32) from %stack.5), (load (s32) from %stack.4)
- ; CHECK: bb.5.bb74:
- ; CHECK: successors: %bb.6(0x04000000), %bb.1(0x7c000000)
- ; CHECK: liveins: $r0, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12, $r2
- ; CHECK: renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 20, 14 /* CC::al */, $noreg
- ; CHECK: t2STRDi8 killed $r9, killed $r4, $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i14), (store (s32) into %ir.i81)
- ; CHECK: t2STRDi8 killed $r6, killed $r0, $r3, 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i84), (store (s32) into %ir.i88)
- ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r5, $cpsr = tSUBi8 killed renamable $r5, 1, 14 /* CC::al */, $noreg
- ; CHECK: $r1 = tMOVr $r12, 14 /* CC::al */, $noreg
- ; CHECK: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
- ; CHECK: bb.6.bb91:
- ; CHECK: $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg
- ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36
+ ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 76
+ ; CHECK-NEXT: $r6, $r5 = t2LDRDi8 $r0, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i7), (load (s32) from %ir.i10)
+ ; CHECK-NEXT: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r3, $r7 = t2LDRDi8 killed $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i), (load (s32) from %ir.i5)
+ ; CHECK-NEXT: renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r8 :: (store (s32) into %stack.9), (store (s32) into %stack.8), (store (s32) into %stack.7)
+ ; CHECK-NEXT: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.9)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.bb12 (align 4):
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.5(0x40000000)
+ ; CHECK-NEXT: liveins: $r1, $r2, $r3, $r5, $r7, $r8, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r9, $r4 = t2LDRDi8 $r3, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i14), (load (s32) from %ir.i20)
+ ; CHECK-NEXT: $r6, $r0 = t2LDRDi8 $r3, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i22), (load (s32) from %ir.i24)
+ ; CHECK-NEXT: dead $lr = t2WLS renamable $r8, %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.bb27:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: t2STRDi8 killed $r3, killed $r5, $sp, 12, 14 /* CC::al */, $noreg :: (store (s32) into %stack.6), (store (s32) into %stack.5)
+ ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i13)
+ ; CHECK-NEXT: tSTRspi killed renamable $r3, $sp, 9, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
+ ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i34)
+ ; CHECK-NEXT: tSTRspi killed renamable $r3, $sp, 8, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1)
+ ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i32)
+ ; CHECK-NEXT: tSTRspi killed renamable $r3, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2)
+ ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i30)
+ ; CHECK-NEXT: t2STRDi8 $r7, killed $r3, $sp, 20, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4), (store (s32) into %stack.3)
+ ; CHECK-NEXT: renamable $r10 = t2LDRi12 killed renamable $r7, 16, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i28)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.bb37 (align 4):
+ ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r4, $r6, $r8, $r9, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1)
+ ; CHECK-NEXT: renamable $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2)
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMULL $r9, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r4, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load (s32) from %stack.3)
+ ; CHECK-NEXT: $r5 = tMOVr killed $r9, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i38)
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r0, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r0 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
+ ; CHECK-NEXT: $lr = tMOVr $r8, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r0, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: early-clobber renamable $r12 = t2STR_POST renamable $r6, killed renamable $r12, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i39)
+ ; CHECK-NEXT: renamable $r8 = t2SUBri killed renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = tMOVr $r7, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r4 = tMOVr $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.bb72:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $r2, $r5, $r6, $r7, $r9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r7 = tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r12, $r8 = t2LDRDi8 $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.8), (load (s32) from %stack.7)
+ ; CHECK-NEXT: tLDMIA killed $r7, 14 /* CC::al */, $noreg, def $r3, def $r5, def $r7 :: (load (s32) from %stack.6), (load (s32) from %stack.5), (load (s32) from %stack.4)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.bb74:
+ ; CHECK-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)
+ ; CHECK-NEXT: liveins: $r0, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 20, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRDi8 killed $r9, killed $r4, $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i14), (store (s32) into %ir.i81)
+ ; CHECK-NEXT: t2STRDi8 killed $r6, killed $r0, $r3, 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i84), (store (s32) into %ir.i88)
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r5, $cpsr = tSUBi8 killed renamable $r5, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r1 = tMOVr $r12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb91:
+ ; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
bb.0.bb:
successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
index 938ae829db4eb8..31e88ea49a1a02 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
@@ -2,7 +2,6 @@
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
--- |
- ; Function Attrs: nounwind
define hidden arm_aapcs_vfpcc void @cond_trip_count(ptr %0, i32 %1, ptr nocapture %2) local_unnamed_addr #1 {
ret void
}
@@ -39,79 +38,93 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: cond_trip_count
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
- ; CHECK: tCMPi8 renamable $r1, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tBcc %bb.2, 2 /* CC::hs */, killed $cpsr
- ; CHECK: bb.1:
- ; CHECK: liveins: $r2
- ; CHECK: renamable $s0 = VLDRS %const.0, 0, 14 /* CC::al */, $noreg
- ; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r12
- ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: t2IT 11, 8, implicit-def $itstate
- ; CHECK: $r12 = tMOVr renamable $r1, 11 /* CC::lt */, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate
- ; CHECK: renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg
- ; CHECK: $r12 = tMOVr $r1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12
- ; CHECK: bb.3:
- ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
- ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4
- ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 0, $noreg, $noreg
- ; CHECK: renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
- ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3
- ; CHECK: bb.4:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4
- ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg
- ; CHECK: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg
- ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0
- ; CHECK: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2DLS killed $r4
- ; CHECK: renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: bb.5:
- ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
- ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $s4
- ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
- ; CHECK: $r4 = VMOVRS $s4, 14 /* CC::al */, $noreg
- ; CHECK: MVE_VPST 2, implicit $vpr
- ; CHECK: renamable $q2 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg
- ; CHECK: renamable $q2 = nnan ninf nsz MVE_VSUB_qr_f32 killed renamable $q2, killed renamable $r4, 1, renamable $vpr, $noreg, undef renamable $q2
- ; CHECK: renamable $q0 = nnan ninf nsz MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg
- ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5
- ; CHECK: bb.6:
- ; CHECK: liveins: $q0, $r1, $r2
- ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0
- ; CHECK: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
- ; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
- ; CHECK: bb.7 (align 4):
- ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8
+ ; CHECK-NEXT: tCMPi8 renamable $r1, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tBcc %bb.2, 2 /* CC::hs */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $s0 = VLDRS %const.0, 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate
+ ; CHECK-NEXT: $r12 = tMOVr renamable $r1, 11 /* CC::lt */, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate
+ ; CHECK-NEXT: renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r12 = tMOVr $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 0, $noreg, $noreg
+ ; CHECK-NEXT: renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0
+ ; CHECK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = t2DLS killed $r4
+ ; CHECK-NEXT: renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5:
+ ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $s4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
+ ; CHECK-NEXT: $r4 = VMOVRS $s4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: MVE_VPST 2, implicit $vpr
+ ; CHECK-NEXT: renamable $q2 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg
+ ; CHECK-NEXT: renamable $q2 = nnan ninf nsz MVE_VSUB_qr_f32 killed renamable $q2, killed renamable $r4, 1, renamable $vpr, $noreg, undef renamable $q2
+ ; CHECK-NEXT: renamable $q0 = nnan ninf nsz MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6:
+ ; CHECK-NEXT: liveins: $q0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0
+ ; CHECK-NEXT: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7 (align 4):
+ ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 4
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $r1, $r2, $r4, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
index 34c8a251e98d2e..4451d27f3c2d3d 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
@@ -222,126 +222,144 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test1
; CHECK: bb.0.bb:
- ; CHECK: successors: %bb.8(0x30000000), %bb.1(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
- ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
- ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40
- ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.8, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.1.bb4:
- ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
- ; CHECK: tBcc %bb.3, 2 /* CC::hs */, killed $cpsr
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2
- ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
- ; CHECK: bb.3.bb12:
- ; CHECK: successors: %bb.4(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: $r12 = tMOVr killed $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: bb.4.bb28:
- ; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3, $r8, $r12
- ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep617)
- ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep418)
- ; CHECK: $lr = tMOVr killed $r12, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep219)
- ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r12 = tMOVr $lr, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep219)
- ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep11)
- ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep14)
- ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: $r11 = t2ADDri $r6, 4, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
- ; CHECK: t2LDMIA killed $r11, 14 /* CC::al */, $noreg, def $r4, def $r10, def $r11 :: (load (s32) from %ir.scevgep9), (load (s32) from %ir.scevgep8), (load (s32) from %ir.scevgep1)
- ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep9)
- ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep12)
- ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep10)
- ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep8)
- ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep5)
- ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
- ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep1)
- ; CHECK: t2CMPri killed renamable $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
- ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
- ; CHECK: bb.5.bb13:
- ; CHECK: successors: %bb.8(0x30000000), %bb.6(0x50000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r8
- ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
- ; CHECK: tCBZ $r5, %bb.8
- ; CHECK: bb.6.bb16:
- ; CHECK: successors: %bb.8(0x40000000), %bb.7(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8
- ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp17)
- ; CHECK: tCMPi8 renamable $r5, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp19)
- ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp22)
- ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 /* CC::al */, $noreg
- ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp22)
- ; CHECK: tBcc %bb.8, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.7.bb57:
- ; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8
- ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tCMPi8 killed renamable $r5, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp58)
- ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp60)
- ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp63)
- ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp63)
- ; CHECK: tBcc %bb.9, 1 /* CC::ne */, killed $cpsr
- ; CHECK: bb.8.bb27:
- ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
- ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
- ; CHECK: bb.9.bb68:
- ; CHECK: liveins: $r0, $r1, $r2, $r8
- ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp69)
- ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp71)
- ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp74)
- ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp74)
- ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
- ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
+ ; CHECK-NEXT: successors: %bb.8(0x30000000), %bb.1(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36
+ ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 40
+ ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.8, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.bb4:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r7 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tSTRspi killed renamable $r7, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
+ ; CHECK-NEXT: tBcc %bb.3, 2 /* CC::hs */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tB %bb.5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.bb12:
+ ; CHECK-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r12 = tMOVr killed $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.bb28:
+ ; CHECK-NEXT: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r8, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep617)
+ ; CHECK-NEXT: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep418)
+ ; CHECK-NEXT: $lr = tMOVr killed $r12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep219)
+ ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r12 = tMOVr $lr, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep219)
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep11)
+ ; CHECK-NEXT: renamable $r6 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep14)
+ ; CHECK-NEXT: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r11 = t2ADDri $r6, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2LDMIA killed $r11, 14 /* CC::al */, $noreg, def $r4, def $r10, def $r11 :: (load (s32) from %ir.scevgep9), (load (s32) from %ir.scevgep8), (load (s32) from %ir.scevgep1)
+ ; CHECK-NEXT: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r4, renamable $r6, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep9)
+ ; CHECK-NEXT: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep12)
+ ; CHECK-NEXT: renamable $r4 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep10)
+ ; CHECK-NEXT: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r4, renamable $r6, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep8)
+ ; CHECK-NEXT: renamable $r4 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep5)
+ ; CHECK-NEXT: renamable $r5 = tLDRi killed renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep1)
+ ; CHECK-NEXT: t2CMPri killed renamable $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: tB %bb.5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.bb13:
+ ; CHECK-NEXT: successors: %bb.8(0x30000000), %bb.6(0x50000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r5 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
+ ; CHECK-NEXT: tCBZ $r5, %bb.8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb16:
+ ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.7(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r5, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp17)
+ ; CHECK-NEXT: tCMPi8 renamable $r5, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp19)
+ ; CHECK-NEXT: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp22)
+ ; CHECK-NEXT: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp22)
+ ; CHECK-NEXT: tBcc %bb.8, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.bb57:
+ ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.9(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r5, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tCMPi8 killed renamable $r5, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp58)
+ ; CHECK-NEXT: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp60)
+ ; CHECK-NEXT: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp63)
+ ; CHECK-NEXT: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp63)
+ ; CHECK-NEXT: tBcc %bb.9, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8.bb27:
+ ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.9.bb68:
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp69)
+ ; CHECK-NEXT: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp71)
+ ; CHECK-NEXT: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp74)
+ ; CHECK-NEXT: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp74)
+ ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
bb.0.bb:
successors: %bb.8(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
index 214eb488a76770..58fa1151013742 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
@@ -223,136 +223,161 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test1
; CHECK: bb.0.bb:
- ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
- ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
- ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40
- ; CHECK: tCBZ $r3, %bb.3
- ; CHECK: bb.1.bb4:
- ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
- ; CHECK: tBcc %bb.4, 2 /* CC::hs */, killed $cpsr
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.6(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2
- ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tB %bb.6, 14 /* CC::al */, $noreg
- ; CHECK: bb.3:
- ; CHECK: successors: %bb.12(0x80000000)
- ; CHECK: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
- ; CHECK: bb.4.bb12:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: dead $lr = t2DLS renamable $r3
- ; CHECK: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: bb.5.bb28:
- ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r8
- ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep617)
- ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep418)
- ; CHECK: dead $r12 = tMOVr $lr, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep219)
- ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep219)
- ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep11)
- ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep14)
- ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: $r11 = t2ADDri $r6, 4, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
- ; CHECK: t2LDMIA killed $r11, 14 /* CC::al */, $noreg, def $r4, def $r10, def $r11 :: (load (s32) from %ir.scevgep9), (load (s32) from %ir.scevgep8), (load (s32) from %ir.scevgep1)
- ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep9)
- ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep12)
- ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep10)
- ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep8)
- ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep5)
- ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
- ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep1)
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5
- ; CHECK: bb.6.bb13:
- ; CHECK: successors: %bb.12(0x30000000), %bb.7(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r8
- ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
- ; CHECK: tCBZ $r5, %bb.12
- ; CHECK: bb.7.bb16:
- ; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8
- ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp17)
- ; CHECK: tCMPi8 renamable $r5, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp19)
- ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp22)
- ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 /* CC::al */, $noreg
- ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp22)
- ; CHECK: tBcc %bb.9, 1 /* CC::ne */, killed $cpsr
- ; CHECK: bb.8:
- ; CHECK: successors: %bb.12(0x80000000)
- ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
- ; CHECK: bb.9.bb57:
- ; CHECK: successors: %bb.10(0x40000000), %bb.11(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8
- ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tCMPi8 killed renamable $r5, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp58)
- ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp60)
- ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp63)
- ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp63)
- ; CHECK: tBcc %bb.11, 1 /* CC::ne */, killed $cpsr
- ; CHECK: bb.10:
- ; CHECK: successors: %bb.12(0x80000000)
- ; CHECK: renamable $lr = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
- ; CHECK: bb.11.bb68:
- ; CHECK: successors: %bb.12(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r8
- ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $lr = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp69)
- ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp71)
- ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp74)
- ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp74)
- ; CHECK: bb.12.bb27:
- ; CHECK: liveins: $lr
- ; CHECK: $r0 = tMOVr killed $lr, 14 /* CC::al */, $noreg
- ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
- ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0
+ ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36
+ ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 40
+ ; CHECK-NEXT: tCBZ $r3, %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.bb4:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r7 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tSTRspi killed renamable $r7, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
+ ; CHECK-NEXT: tBcc %bb.4, 2 /* CC::hs */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.6(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tB %bb.6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: successors: %bb.12(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tB %bb.12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.bb12:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: dead $lr = t2DLS renamable $r3
+ ; CHECK-NEXT: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.bb28:
+ ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep617)
+ ; CHECK-NEXT: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep418)
+ ; CHECK-NEXT: dead $r12 = tMOVr $lr, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep219)
+ ; CHECK-NEXT: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep219)
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep11)
+ ; CHECK-NEXT: renamable $r6 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep14)
+ ; CHECK-NEXT: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r11 = t2ADDri $r6, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2LDMIA killed $r11, 14 /* CC::al */, $noreg, def $r4, def $r10, def $r11 :: (load (s32) from %ir.scevgep9), (load (s32) from %ir.scevgep8), (load (s32) from %ir.scevgep1)
+ ; CHECK-NEXT: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r4, renamable $r6, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep9)
+ ; CHECK-NEXT: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep12)
+ ; CHECK-NEXT: renamable $r4 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep10)
+ ; CHECK-NEXT: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r4, renamable $r6, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep8)
+ ; CHECK-NEXT: renamable $r4 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep5)
+ ; CHECK-NEXT: renamable $r5 = tLDRi killed renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep1)
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb13:
+ ; CHECK-NEXT: successors: %bb.12(0x30000000), %bb.7(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r5 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
+ ; CHECK-NEXT: tCBZ $r5, %bb.12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.bb16:
+ ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.9(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r5, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp17)
+ ; CHECK-NEXT: tCMPi8 renamable $r5, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp19)
+ ; CHECK-NEXT: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp22)
+ ; CHECK-NEXT: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp22)
+ ; CHECK-NEXT: tBcc %bb.9, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8:
+ ; CHECK-NEXT: successors: %bb.12(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tB %bb.12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.9.bb57:
+ ; CHECK-NEXT: successors: %bb.10(0x40000000), %bb.11(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r5, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tCMPi8 killed renamable $r5, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp58)
+ ; CHECK-NEXT: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp60)
+ ; CHECK-NEXT: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp63)
+ ; CHECK-NEXT: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp63)
+ ; CHECK-NEXT: tBcc %bb.11, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.10:
+ ; CHECK-NEXT: successors: %bb.12(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $lr = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tB %bb.12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.11.bb68:
+ ; CHECK-NEXT: successors: %bb.12(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $lr = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp69)
+ ; CHECK-NEXT: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp71)
+ ; CHECK-NEXT: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp74)
+ ; CHECK-NEXT: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp74)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.12.bb27:
+ ; CHECK-NEXT: liveins: $lr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r0 = tMOVr killed $lr, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0
bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir
index 8a1a3ed66c7936..14854e1c924a7f 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir
@@ -223,135 +223,160 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test1
; CHECK: bb.0.bb:
- ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
- ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
- ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40
- ; CHECK: tCBZ $r3, %bb.3
- ; CHECK: bb.1.bb4:
- ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
- ; CHECK: tBcc %bb.4, 2 /* CC::hs */, killed $cpsr
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.6(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2
- ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tB %bb.6, 14 /* CC::al */, $noreg
- ; CHECK: bb.3:
- ; CHECK: successors: %bb.12(0x80000000)
- ; CHECK: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
- ; CHECK: bb.4.bb12:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: dead $lr = t2DLS renamable $r3
- ; CHECK: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: bb.5.bb28:
- ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r8
- ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep617)
- ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep418)
- ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep219)
- ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep219)
- ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep11)
- ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep14)
- ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: $r11 = t2ADDri $r6, 4, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
- ; CHECK: t2LDMIA killed $r11, 14 /* CC::al */, $noreg, def $r4, def $r10, def $r11 :: (load (s32) from %ir.scevgep9), (load (s32) from %ir.scevgep8), (load (s32) from %ir.scevgep1)
- ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep9)
- ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep12)
- ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep10)
- ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep8)
- ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep5)
- ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
- ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep1)
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5
- ; CHECK: bb.6.bb13:
- ; CHECK: successors: %bb.12(0x30000000), %bb.7(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r8
- ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
- ; CHECK: tCBZ $r5, %bb.12
- ; CHECK: bb.7.bb16:
- ; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r5, $r8
- ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp17)
- ; CHECK: tCMPi8 renamable $r5, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp19)
- ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp22)
- ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 /* CC::al */, $noreg
- ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp22)
- ; CHECK: tBcc %bb.9, 1 /* CC::ne */, killed $cpsr
- ; CHECK: bb.8:
- ; CHECK: successors: %bb.12(0x80000000)
- ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
- ; CHECK: bb.9.bb57:
- ; CHECK: successors: %bb.10(0x40000000), %bb.11(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8
- ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tCMPi8 killed renamable $r5, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp58)
- ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp60)
- ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp63)
- ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp63)
- ; CHECK: tBcc %bb.11, 1 /* CC::ne */, killed $cpsr
- ; CHECK: bb.10:
- ; CHECK: successors: %bb.12(0x80000000)
- ; CHECK: renamable $lr = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tB %bb.12, 14 /* CC::al */, $noreg
- ; CHECK: bb.11.bb68:
- ; CHECK: successors: %bb.12(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r8
- ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $lr = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp69)
- ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp71)
- ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp74)
- ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp74)
- ; CHECK: bb.12.bb27:
- ; CHECK: liveins: $lr
- ; CHECK: $r0 = tMOVr killed $lr, 14 /* CC::al */, $noreg
- ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
- ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0
+ ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36
+ ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 40
+ ; CHECK-NEXT: tCBZ $r3, %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.bb4:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r7 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tSTRspi killed renamable $r7, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
+ ; CHECK-NEXT: tBcc %bb.4, 2 /* CC::hs */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.6(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tB %bb.6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: successors: %bb.12(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $lr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tB %bb.12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.bb12:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: dead $lr = t2DLS renamable $r3
+ ; CHECK-NEXT: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.bb28:
+ ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep617)
+ ; CHECK-NEXT: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep418)
+ ; CHECK-NEXT: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep219)
+ ; CHECK-NEXT: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep219)
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep11)
+ ; CHECK-NEXT: renamable $r6 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep14)
+ ; CHECK-NEXT: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r11 = t2ADDri $r6, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2LDMIA killed $r11, 14 /* CC::al */, $noreg, def $r4, def $r10, def $r11 :: (load (s32) from %ir.scevgep9), (load (s32) from %ir.scevgep8), (load (s32) from %ir.scevgep1)
+ ; CHECK-NEXT: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r4, renamable $r6, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep9)
+ ; CHECK-NEXT: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep12)
+ ; CHECK-NEXT: renamable $r4 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep10)
+ ; CHECK-NEXT: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r4, renamable $r6, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep8)
+ ; CHECK-NEXT: renamable $r4 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep5)
+ ; CHECK-NEXT: renamable $r5 = tLDRi killed renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep1)
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb13:
+ ; CHECK-NEXT: successors: %bb.12(0x30000000), %bb.7(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r5 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
+ ; CHECK-NEXT: tCBZ $r5, %bb.12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.bb16:
+ ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.9(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r5, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp17)
+ ; CHECK-NEXT: tCMPi8 renamable $r5, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp19)
+ ; CHECK-NEXT: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp22)
+ ; CHECK-NEXT: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp22)
+ ; CHECK-NEXT: tBcc %bb.9, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8:
+ ; CHECK-NEXT: successors: %bb.12(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tB %bb.12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.9.bb57:
+ ; CHECK-NEXT: successors: %bb.10(0x40000000), %bb.11(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r5, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tCMPi8 killed renamable $r5, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp58)
+ ; CHECK-NEXT: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp60)
+ ; CHECK-NEXT: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp63)
+ ; CHECK-NEXT: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp63)
+ ; CHECK-NEXT: tBcc %bb.11, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.10:
+ ; CHECK-NEXT: successors: %bb.12(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $lr = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tB %bb.12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.11.bb68:
+ ; CHECK-NEXT: successors: %bb.12(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $lr = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp69)
+ ; CHECK-NEXT: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp71)
+ ; CHECK-NEXT: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.tmp74)
+ ; CHECK-NEXT: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.tmp74)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.12.bb27:
+ ; CHECK-NEXT: liveins: $lr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r0 = tMOVr killed $lr, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0
bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
index 3a0bc9d50a1d9f..8abb2ab8ccb342 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
@@ -202,76 +202,86 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test_debug
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x50000000), %bb.5(0x30000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10
- ; CHECK: DBG_VALUE $r0, $noreg, !23, !DIExpression(), debug-location !32
- ; CHECK: DBG_VALUE $r1, $noreg, !24, !DIExpression(), debug-location !32
- ; CHECK: DBG_VALUE $r2, $noreg, !25, !DIExpression(), debug-location !32
- ; CHECK: DBG_VALUE $r3, $noreg, !26, !DIExpression(), debug-location !32
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
- ; CHECK: $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
- ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
- ; CHECK: $r5 = tMOVr killed $r2, 14 /* CC::al */, $noreg
- ; CHECK: DBG_VALUE $r5, $noreg, !25, !DIExpression(), debug-location !32
- ; CHECK: $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg, debug-location !33
- ; CHECK: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
- ; CHECK: DBG_VALUE $r8, $noreg, !26, !DIExpression(), debug-location !32
- ; CHECK: $r9 = tMOVr $r1, 14 /* CC::al */, $noreg
- ; CHECK: DBG_VALUE $r9, $noreg, !24, !DIExpression(), debug-location !32
- ; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: DBG_VALUE 0, $noreg, !29, !DIExpression(), debug-location !32
- ; CHECK: DBG_VALUE $r10, $noreg, !23, !DIExpression(), debug-location !32
- ; CHECK: tBL 14 /* CC::al */, $noreg, @get_input, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit-def $sp, implicit-def dead $r0, debug-location !33
- ; CHECK: DBG_VALUE 0, $noreg, !30, !DIExpression(), debug-location !32
- ; CHECK: DBG_VALUE $noreg, $noreg, !28, !DIExpression(), debug-location !32
- ; CHECK: t2CMPri renamable $r10, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !37
- ; CHECK: tBcc %bb.5, 11 /* CC::lt */, killed $cpsr, debug-location !37
- ; CHECK: bb.1.for.cond1.preheader.us.preheader:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: liveins: $r5, $r8, $r9, $r10
- ; CHECK: renamable $r12 = t2LSLri renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg, debug-location !37
- ; CHECK: renamable $r1, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: bb.2.for.cond1.preheader.us:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: liveins: $r1, $r5, $r8, $r9, $r10, $r12
- ; CHECK: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32
- ; CHECK: DBG_VALUE 0, $noreg, !31, !DIExpression(), debug-location !32
- ; CHECK: renamable $r2 = t2LDRs renamable $r9, renamable $r1, 2, 14 /* CC::al */, $noreg, debug-location !41 :: (load (s32) from %ir.arrayidx7.us)
- ; CHECK: $r3 = tMOVr $r5, 14 /* CC::al */, $noreg, debug-location !32
- ; CHECK: $r0 = tMOVr $r8, 14 /* CC::al */, $noreg, debug-location !32
- ; CHECK: dead $lr = tMOVr $r10, 14 /* CC::al */, $noreg, debug-location !32
- ; CHECK: $lr = t2DLS renamable $r10, debug-location !42
- ; CHECK: bb.3.for.body3.us:
- ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r8, $r9, $r10, $r12
- ; CHECK: DBG_VALUE $noreg, $noreg, !31, !DIExpression(), debug-location !32
- ; CHECK: renamable $r6, renamable $r3 = t2LDRSH_POST killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !43 :: (load (s16) from %ir.lsr.iv5)
- ; CHECK: renamable $r4, renamable $r0 = t2LDRSH_POST killed renamable $r0, 2, 14 /* CC::al */, $noreg, debug-location !44 :: (load (s16) from %ir.lsr.iv1)
- ; CHECK: renamable $r2 = nsw t2SMLABB killed renamable $r4, killed renamable $r6, killed renamable $r2, 14 /* CC::al */, $noreg, debug-location !41
- ; CHECK: DBG_VALUE $noreg, $noreg, !31, !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), debug-location !32
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3, debug-location !42
- ; CHECK: bb.4.for.cond1.for.inc9_crit_edge.us:
- ; CHECK: successors: %bb.5(0x04000000), %bb.2(0x7c000000)
- ; CHECK: liveins: $r1, $r2, $r5, $r8, $r9, $r10, $r12
- ; CHECK: t2STRs killed renamable $r2, renamable $r9, renamable $r1, 2, 14 /* CC::al */, $noreg, debug-location !41 :: (store (s32) into %ir.8)
- ; CHECK: renamable $r1, dead $cpsr = nuw nsw tADDi8 killed renamable $r1, 1, 14 /* CC::al */, $noreg, debug-location !49
- ; CHECK: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32
- ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r12, 14 /* CC::al */, $noreg, debug-location !37
- ; CHECK: tCMPhir renamable $r1, renamable $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !37
- ; CHECK: tBcc %bb.2, 1 /* CC::ne */, killed $cpsr, debug-location !37
- ; CHECK: bb.5.for.end11:
- ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10, debug-location !52
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, debug-location !52
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.5(0x30000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: DBG_VALUE $r0, $noreg, !23, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !24, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !25, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: DBG_VALUE $r3, $noreg, !26, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -20
+ ; CHECK-NEXT: $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
+ ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -28
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -32
+ ; CHECK-NEXT: $r5 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: DBG_VALUE $r5, $noreg, !25, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg, debug-location !33
+ ; CHECK-NEXT: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: DBG_VALUE $r8, $noreg, !26, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: $r9 = tMOVr $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: DBG_VALUE $r9, $noreg, !24, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: DBG_VALUE 0, $noreg, !29, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: DBG_VALUE $r10, $noreg, !23, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @get_input, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit-def $sp, implicit-def dead $r0, debug-location !33
+ ; CHECK-NEXT: DBG_VALUE 0, $noreg, !30, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: DBG_VALUE $noreg, $noreg, !28, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: t2CMPri renamable $r10, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !37
+ ; CHECK-NEXT: tBcc %bb.5, 11 /* CC::lt */, killed $cpsr, debug-location !37
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.for.cond1.preheader.us.preheader:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $r5, $r8, $r9, $r10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r12 = t2LSLri renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg, debug-location !37
+ ; CHECK-NEXT: renamable $r1, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.for.cond1.preheader.us:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: liveins: $r1, $r5, $r8, $r9, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: DBG_VALUE 0, $noreg, !31, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: renamable $r2 = t2LDRs renamable $r9, renamable $r1, 2, 14 /* CC::al */, $noreg, debug-location !41 :: (load (s32) from %ir.arrayidx7.us)
+ ; CHECK-NEXT: $r3 = tMOVr $r5, 14 /* CC::al */, $noreg, debug-location !32
+ ; CHECK-NEXT: $r0 = tMOVr $r8, 14 /* CC::al */, $noreg, debug-location !32
+ ; CHECK-NEXT: dead $lr = tMOVr $r10, 14 /* CC::al */, $noreg, debug-location !32
+ ; CHECK-NEXT: $lr = t2DLS renamable $r10, debug-location !42
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.for.body3.us:
+ ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r8, $r9, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: DBG_VALUE $noreg, $noreg, !31, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: renamable $r6, renamable $r3 = t2LDRSH_POST killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !43 :: (load (s16) from %ir.lsr.iv5)
+ ; CHECK-NEXT: renamable $r4, renamable $r0 = t2LDRSH_POST killed renamable $r0, 2, 14 /* CC::al */, $noreg, debug-location !44 :: (load (s16) from %ir.lsr.iv1)
+ ; CHECK-NEXT: renamable $r2 = nsw t2SMLABB killed renamable $r4, killed renamable $r6, killed renamable $r2, 14 /* CC::al */, $noreg, debug-location !41
+ ; CHECK-NEXT: DBG_VALUE $noreg, $noreg, !31, !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), debug-location !32
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.3, debug-location !42
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.for.cond1.for.inc9_crit_edge.us:
+ ; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.2(0x7c000000)
+ ; CHECK-NEXT: liveins: $r1, $r2, $r5, $r8, $r9, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: t2STRs killed renamable $r2, renamable $r9, renamable $r1, 2, 14 /* CC::al */, $noreg, debug-location !41 :: (store (s32) into %ir.8)
+ ; CHECK-NEXT: renamable $r1, dead $cpsr = nuw nsw tADDi8 killed renamable $r1, 1, 14 /* CC::al */, $noreg, debug-location !49
+ ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32
+ ; CHECK-NEXT: renamable $r5 = tADDhirr killed renamable $r5, renamable $r12, 14 /* CC::al */, $noreg, debug-location !37
+ ; CHECK-NEXT: tCMPhir renamable $r1, renamable $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !37
+ ; CHECK-NEXT: tBcc %bb.2, 1 /* CC::ne */, killed $cpsr, debug-location !37
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.for.end11:
+ ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10, debug-location !52
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, debug-location !52
bb.0.entry:
successors: %bb.1(0x50000000), %bb.5(0x30000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
index 070a20734c2ebe..f07d1beecdbbe1 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
@@ -214,150 +214,179 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: matrix_test
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x50000000), %bb.12(0x30000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
- ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 32
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -24
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -28
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -32
- ; CHECK: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: t2Bcc %bb.12, 11 /* CC::lt */, killed $cpsr
- ; CHECK: bb.1.for.body.i.preheader:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: $r5 = tMOVr killed $r2, 14 /* CC::al */, $noreg
- ; CHECK: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
- ; CHECK: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2 = IMPLICIT_DEF
- ; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2DLS killed renamable $r0
- ; CHECK: bb.2.for.body.i:
- ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- ; CHECK: liveins: $lr, $r1, $r2, $r4, $r5, $r6, $r8, $r10
- ; CHECK: renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv15)
- ; CHECK: renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r7 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
- ; CHECK: tCMPi8 killed renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
- ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: t2IT 12, 8, implicit-def $itstate
- ; CHECK: $r2 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
- ; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
- ; CHECK: bb.3.c.exit:
- ; CHECK: successors: %bb.4(0x50000000), %bb.14(0x30000000)
- ; CHECK: liveins: $r4, $r5, $r6, $r8, $r10
- ; CHECK: renamable $r0 = tSXTH killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
- ; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: t2CMPri $r10, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.14, 11 /* CC::lt */, killed $cpsr
- ; CHECK: bb.4.for.cond4.preheader.us.preheader:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $r4, $r5, $r7, $r8, $r10, $r12
- ; CHECK: renamable $r0 = t2ADDri $r10, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r0 = t2BICri killed renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3 = t2LSLri $r10, 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: bb.5.for.cond4.preheader.us:
- ; CHECK: successors: %bb.6(0x80000000)
- ; CHECK: liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
- ; CHECK: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.arrayidx12.us)
- ; CHECK: $q1 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q1
- ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg
- ; CHECK: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14 /* CC::al */, $noreg
- ; CHECK: $r6 = tMOVr $r5, 14 /* CC::al */, $noreg
- ; CHECK: $r1 = tMOVr $r8, 14 /* CC::al */, $noreg
- ; CHECK: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2DLS renamable $r0
- ; CHECK: bb.6.vector.body:
- ; CHECK: successors: %bb.6(0x7c000000), %bb.7(0x04000000)
- ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12
- ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
- ; CHECK: $q2 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q2
- ; CHECK: MVE_VPST 4, implicit $vpr
- ; CHECK: renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1012, align 2)
- ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv46, align 2)
- ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
- ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, $noreg, undef renamable $q1
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.6
- ; CHECK: bb.7.middle.block:
- ; CHECK: successors: %bb.8(0x04000000), %bb.5(0x7c000000)
- ; CHECK: liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
- ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg, $noreg
- ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr, $noreg
- ; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg
- ; CHECK: t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.27)
- ; CHECK: renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14 /* CC::al */, $noreg
- ; CHECK: tCMPhir renamable $r7, $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.5, 1 /* CC::ne */, killed $cpsr
- ; CHECK: bb.8.for.end16:
- ; CHECK: successors: %bb.9(0x50000000), %bb.13(0x30000000)
- ; CHECK: liveins: $lr, $r4, $r12
- ; CHECK: t2CMPri renamable $lr, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.13, 11 /* CC::lt */, killed $cpsr
- ; CHECK: bb.9.for.body.i57.preheader:
- ; CHECK: successors: %bb.10(0x80000000)
- ; CHECK: liveins: $lr, $r4, $r12
- ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r1 = IMPLICIT_DEF
- ; CHECK: bb.10.for.body.i57:
- ; CHECK: successors: %bb.10(0x7c000000), %bb.11(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r4, $r12
- ; CHECK: renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv1)
- ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
- ; CHECK: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
- ; CHECK: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: t2IT 12, 8, implicit-def $itstate
- ; CHECK: $r1 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate
- ; CHECK: renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.10
- ; CHECK: bb.11.c.exit59.loopexit:
- ; CHECK: successors: %bb.14(0x80000000)
- ; CHECK: liveins: $r0, $r12
- ; CHECK: renamable $r7 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg
- ; CHECK: tB %bb.14, 14 /* CC::al */, $noreg
- ; CHECK: bb.12.c.exit.thread:
- ; CHECK: successors: %bb.14(0x80000000)
- ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
- ; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
- ; CHECK: tB %bb.14, 14 /* CC::al */, $noreg
- ; CHECK: bb.13:
- ; CHECK: successors: %bb.14(0x80000000)
- ; CHECK: liveins: $r12
- ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: bb.14.c.exit59:
- ; CHECK: liveins: $r7, $r12
- ; CHECK: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg
- ; CHECK: $r1 = tMOVr killed $r12, 14 /* CC::al */, $noreg
- ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr
- ; CHECK: tTAILJMPdND @crc16, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.12(0x30000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 32
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -28
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -32
+ ; CHECK-NEXT: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: t2Bcc %bb.12, 11 /* CC::lt */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.for.body.i.preheader:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r5 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2 = IMPLICIT_DEF
+ ; CHECK-NEXT: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = t2DLS killed renamable $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.for.body.i:
+ ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r1, $r2, $r4, $r5, $r6, $r8, $r10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv15)
+ ; CHECK-NEXT: renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r7 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
+ ; CHECK-NEXT: tCMPi8 killed renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
+ ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate
+ ; CHECK-NEXT: $r2 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
+ ; CHECK-NEXT: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.c.exit:
+ ; CHECK-NEXT: successors: %bb.4(0x50000000), %bb.14(0x30000000)
+ ; CHECK-NEXT: liveins: $r4, $r5, $r6, $r8, $r10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r0 = tSXTH killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
+ ; CHECK-NEXT: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2CMPri $r10, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.14, 11 /* CC::lt */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.for.cond4.preheader.us.preheader:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $r4, $r5, $r7, $r8, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r0 = t2ADDri $r10, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $lr = tMOVr $r10, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r0 = t2BICri killed renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3 = t2LSLri $r10, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.for.cond4.preheader.us:
+ ; CHECK-NEXT: successors: %bb.6(0x80000000)
+ ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.arrayidx12.us)
+ ; CHECK-NEXT: $q1 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q1
+ ; CHECK-NEXT: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r6 = tMOVr $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r1 = tMOVr $r8, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = t2DLS renamable $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.vector.body:
+ ; CHECK-NEXT: successors: %bb.6(0x7c000000), %bb.7(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
+ ; CHECK-NEXT: $q2 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q2
+ ; CHECK-NEXT: MVE_VPST 4, implicit $vpr
+ ; CHECK-NEXT: renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1012, align 2)
+ ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv46, align 2)
+ ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
+ ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, $noreg, undef renamable $q1
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.middle.block:
+ ; CHECK-NEXT: successors: %bb.8(0x04000000), %bb.5(0x7c000000)
+ ; CHECK-NEXT: liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr, $noreg
+ ; CHECK-NEXT: $lr = tMOVr $r10, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.27)
+ ; CHECK-NEXT: renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tCMPhir renamable $r7, $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.5, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8.for.end16:
+ ; CHECK-NEXT: successors: %bb.9(0x50000000), %bb.13(0x30000000)
+ ; CHECK-NEXT: liveins: $lr, $r4, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: t2CMPri renamable $lr, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.13, 11 /* CC::lt */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.9.for.body.i57.preheader:
+ ; CHECK-NEXT: successors: %bb.10(0x80000000)
+ ; CHECK-NEXT: liveins: $lr, $r4, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r1 = IMPLICIT_DEF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.10.for.body.i57:
+ ; CHECK-NEXT: successors: %bb.10(0x7c000000), %bb.11(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r4, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv1)
+ ; CHECK-NEXT: renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
+ ; CHECK-NEXT: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
+ ; CHECK-NEXT: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate
+ ; CHECK-NEXT: $r1 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate
+ ; CHECK-NEXT: renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.11.c.exit59.loopexit:
+ ; CHECK-NEXT: successors: %bb.14(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r7 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tB %bb.14, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.12.c.exit.thread:
+ ; CHECK-NEXT: successors: %bb.14(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
+ ; CHECK-NEXT: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tB %bb.14, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.13:
+ ; CHECK-NEXT: successors: %bb.14(0x80000000)
+ ; CHECK-NEXT: liveins: $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.14.c.exit59:
+ ; CHECK-NEXT: liveins: $r7, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r1 = tMOVr killed $r12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr
+ ; CHECK-NEXT: tTAILJMPdND @crc16, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1
bb.0.entry:
successors: %bb.1(0x50000000), %bb.12(0x30000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
index af76970f18da8c..57101b15243fb6 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
@@ -73,25 +73,18 @@
ret void
}
- ; Function Attrs: nounwind readnone
declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
- ; Function Attrs: nounwind readnone
declare <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
- ; Function Attrs: nounwind readnone
declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
- ; Function Attrs: argmemonly nounwind readonly willreturn
declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) #2
- ; Function Attrs: nounwind readnone
declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
- ; Function Attrs: noduplicate nounwind
declare i32 @llvm.start.loop.iterations.i32(i32) #3
- ; Function Attrs: noduplicate nounwind
declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #3
attributes #0 = { "target-features"="+mve.fp" }
@@ -148,55 +141,64 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: arm_var_f32_mve
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
- ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
- ; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
- ; CHECK: $r4 = tMOVr $lr, 14 /* CC::al */, $noreg
- ; CHECK: bb.1.do.body.i:
- ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
- ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r4, $r12
- ; CHECK: renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.0.i2, align 4)
- ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
- ; CHECK: bb.2.arm_mean_f32_mve.exit:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4
- ; CHECK: $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg
- ; CHECK: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0
- ; CHECK: $lr = t2DLS killed $r4
- ; CHECK: renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg
- ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
- ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
- ; CHECK: bb.3.do.body:
- ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
- ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3
- ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
- ; CHECK: MVE_VPST 2, implicit $vpr
- ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.01, align 4)
- ; CHECK: renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2
- ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3
- ; CHECK: bb.4.do.end:
- ; CHECK: liveins: $q0, $r1, $r2
- ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0
- ; CHECK: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
- ; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult)
- ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8
+ ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3
+ ; CHECK-NEXT: $r4 = tMOVr $lr, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.do.body.i:
+ ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r4, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.0.i2, align 4)
+ ; CHECK-NEXT: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.arm_mean_f32_mve.exit:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0
+ ; CHECK-NEXT: $lr = t2DLS killed $r4
+ ; CHECK-NEXT: renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
+ ; CHECK-NEXT: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.do.body:
+ ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: MVE_VPST 2, implicit $vpr
+ ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.01, align 4)
+ ; CHECK-NEXT: renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2
+ ; CHECK-NEXT: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.do.end:
+ ; CHECK-NEXT: liveins: $q0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0
+ ; CHECK-NEXT: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult)
+ ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry:
successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r4, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir
index f17496c3d1653d..199e222ccf6aa0 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir
@@ -192,118 +192,138 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: multi_cond_iter_count
; CHECK: bb.0 (%ir-block.4):
- ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
- ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
- ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
- ; CHECK: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg
- ; CHECK: t2IT 1, 8, implicit-def $itstate
- ; CHECK: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
- ; CHECK: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: t2IT 0, 8, implicit-def $itstate
- ; CHECK: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
- ; CHECK: renamable $r3 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr
- ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.1 (%ir-block.11):
- ; CHECK: successors: %bb.2(0x55555555), %bb.5(0x2aaaaaab)
- ; CHECK: liveins: $r0, $r1, $r3
- ; CHECK: renamable $r2 = t2ADDrs renamable $r1, renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tCMPr killed renamable $r2, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: t2IT 8, 4, implicit-def $itstate
- ; CHECK: renamable $r2 = t2ADDrs renamable $r0, renamable $r3, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate
- ; CHECK: tCMPr killed renamable $r2, renamable $r1, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
- ; CHECK: tBcc %bb.5, 8 /* CC::hi */, killed $cpsr
- ; CHECK: bb.2 (%ir-block.32):
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r3
- ; CHECK: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
- ; CHECK: bb.3 (%ir-block.33):
- ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2
- ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg
- ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg
- ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg
- ; CHECK: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3
- ; CHECK: bb.4 (%ir-block.64):
- ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
- ; CHECK: bb.5 (%ir-block.23):
- ; CHECK: successors: %bb.6(0x40000000), %bb.7(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r3
- ; CHECK: renamable $r2, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r12 = t2ANDri renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.7, 2 /* CC::hs */, killed $cpsr
- ; CHECK: bb.6:
- ; CHECK: successors: %bb.9(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r12
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: tB %bb.9, 14 /* CC::al */, $noreg
- ; CHECK: bb.7 (%ir-block.31):
- ; CHECK: successors: %bb.8(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r3, $r12
- ; CHECK: renamable $r2 = t2BICri killed renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: bb.8 (%ir-block.65):
- ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
- ; CHECK: renamable $r4 = tLDRr renamable $r1, $r2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r5 = tLDRr renamable $r0, $r2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4, dead $cpsr = nsw tMUL killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: $r10, $r8 = t2LDRDi8 $r5, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 12, 14 /* CC::al */, $noreg
- ; CHECK: tSTRr killed renamable $r4, renamable $r0, $r2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = tLDRi renamable $r4, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = nsw t2MUL killed renamable $r10, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r6, renamable $r5, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = tLDRi renamable $r4, 2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r6 = nsw t2MUL killed renamable $r8, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r6, renamable $r5, 2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4 = tLDRi killed renamable $r4, 3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4 = nsw t2MUL killed renamable $r9, killed renamable $r4, 14 /* CC::al */, $noreg
- ; CHECK: tSTRi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.8
- ; CHECK: bb.9 (%ir-block.49):
- ; CHECK: successors: %bb.4(0x40000000), %bb.10(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r3, $r12
- ; CHECK: t2CMPri killed renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.10 (%ir-block.52):
- ; CHECK: liveins: $r0, $r1, $r3
- ; CHECK: renamable $r12 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r12 = nsw t2MUL killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $lr = t2LDRs renamable $r0, renamable $r2, 2, 14 /* CC::al */, $noreg
- ; CHECK: t2STRs killed renamable $r12, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r2, 2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r1 = nsw t2MUL killed renamable $lr, killed renamable $r1, 14 /* CC::al */, $noreg
- ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r2, 2, 14 /* CC::al */, $noreg
- ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
+ ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -20
+ ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
+ ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -28
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -32
+ ; CHECK-NEXT: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2IT 1, 8, implicit-def $itstate
+ ; CHECK-NEXT: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
+ ; CHECK-NEXT: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate
+ ; CHECK-NEXT: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
+ ; CHECK-NEXT: renamable $r3 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr
+ ; CHECK-NEXT: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1 (%ir-block.11):
+ ; CHECK-NEXT: successors: %bb.2(0x55555555), %bb.5(0x2aaaaaab)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r2 = t2ADDrs renamable $r1, renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tCMPr killed renamable $r2, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: t2IT 8, 4, implicit-def $itstate
+ ; CHECK-NEXT: renamable $r2 = t2ADDrs renamable $r0, renamable $r3, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate
+ ; CHECK-NEXT: tCMPr killed renamable $r2, renamable $r1, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
+ ; CHECK-NEXT: tBcc %bb.5, 8 /* CC::hi */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2 (%ir-block.32):
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3 (%ir-block.33):
+ ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg
+ ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg
+ ; CHECK-NEXT: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4 (%ir-block.64):
+ ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5 (%ir-block.23):
+ ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.7(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r12 = t2ANDri renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.7, 2 /* CC::hs */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6:
+ ; CHECK-NEXT: successors: %bb.9(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tB %bb.9, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7 (%ir-block.31):
+ ; CHECK-NEXT: successors: %bb.8(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r3, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8 (%ir-block.65):
+ ; CHECK-NEXT: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r4 = tLDRr renamable $r1, $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r5 = tLDRr renamable $r0, $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tMUL killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r10, $r8 = t2LDRDi8 $r5, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r9 = t2LDRi12 renamable $r5, 12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRr killed renamable $r4, renamable $r0, $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = tLDRi renamable $r4, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = nsw t2MUL killed renamable $r10, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r6, renamable $r5, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = tLDRi renamable $r4, 2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r6 = nsw t2MUL killed renamable $r8, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r6, renamable $r5, 2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4 = tLDRi killed renamable $r4, 3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4 = nsw t2MUL killed renamable $r9, killed renamable $r4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.9 (%ir-block.49):
+ ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.10(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r3, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: t2CMPri killed renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.10 (%ir-block.52):
+ ; CHECK-NEXT: liveins: $r0, $r1, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r12 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r12 = nsw t2MUL killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $lr = t2LDRs renamable $r0, renamable $r2, 2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r12, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r1 = t2LDRs killed renamable $r1, renamable $r2, 2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r1 = nsw t2MUL killed renamable $lr, killed renamable $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r2, 2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0 (%ir-block.4):
successors: %bb.4(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir
index 6e8ad0877f1c2e..a86eec780b7f4c 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir
@@ -80,7 +80,6 @@
for.cond.cleanup6: ; preds = %vector.body38, %entry, %for.cond4.preheader
ret void
}
- ; Function Attrs: nofree norecurse nounwind
define dso_local arm_aapcs_vfpcc void @test2(i32* noalias nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr {
entry:
%div = lshr i32 %N, 1
@@ -160,7 +159,6 @@
for.cond.cleanup6: ; preds = %vector.body38, %for.cond4.preheader
ret void
}
- ; Function Attrs: nofree norecurse nounwind
define dso_local arm_aapcs_vfpcc void @test3(i32* noalias nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr {
entry:
%cmp54 = icmp eq i32 %N, 0
@@ -346,60 +344,72 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test1
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.6(0x30000000), %bb.1(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
- ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
- ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24
- ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.1.vector.ph:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg
- ; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg
- ; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4
- ; CHECK: bb.2.vector.body:
- ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
- ; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4)
- ; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4)
- ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4)
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
- ; CHECK: bb.3.for.cond4.preheader:
- ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: tCBZ $r3, %bb.6
- ; CHECK: bb.4.vector.ph39:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
- ; CHECK: bb.5.vector.body38:
- ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r12
- ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv55, align 4)
- ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4)
- ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4)
- ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4)
- ; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
- ; CHECK: bb.6.for.cond.cleanup6:
- ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
+ ; CHECK-NEXT: successors: %bb.6(0x30000000), %bb.1(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -20
+ ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
+ ; CHECK-NEXT: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -24
+ ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.vector.ph:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.vector.body:
+ ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4)
+ ; CHECK-NEXT: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4)
+ ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4)
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.for.cond4.preheader:
+ ; CHECK-NEXT: successors: %bb.6(0x30000000), %bb.4(0x50000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: tCBZ $r3, %bb.6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.vector.ph39:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.vector.body38:
+ ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv55, align 4)
+ ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4)
+ ; CHECK-NEXT: renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4)
+ ; CHECK-NEXT: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4)
+ ; CHECK-NEXT: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.for.cond.cleanup6:
+ ; CHECK-NEXT: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0.entry:
successors: %bb.6(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8
@@ -549,61 +559,73 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test2
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
- ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
- ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24
- ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.1.vector.ph:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $r5 = tMOVr $r1, 14 /* CC::al */, $noreg
- ; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4
- ; CHECK: bb.2.vector.body:
- ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
- ; CHECK: renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4)
- ; CHECK: renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4)
- ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4)
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
- ; CHECK: bb.3.for.cond4.preheader:
- ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: tCBZ $r3, %bb.6
- ; CHECK: bb.4.vector.ph39:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
- ; CHECK: bb.5.vector.body38:
- ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4
- ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv55, align 4)
- ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4)
- ; CHECK: renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4)
- ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4)
- ; CHECK: $r0 = tMOVr $r4, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
- ; CHECK: bb.6.for.cond.cleanup6:
- ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
+ ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -20
+ ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
+ ; CHECK-NEXT: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -24
+ ; CHECK-NEXT: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.vector.ph:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r5 = tMOVr $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.vector.body:
+ ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4)
+ ; CHECK-NEXT: renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4)
+ ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4)
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.for.cond4.preheader:
+ ; CHECK-NEXT: successors: %bb.6(0x30000000), %bb.4(0x50000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: tCBZ $r3, %bb.6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.vector.ph39:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.vector.body38:
+ ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv55, align 4)
+ ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4)
+ ; CHECK-NEXT: renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4)
+ ; CHECK-NEXT: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4)
+ ; CHECK-NEXT: $r0 = tMOVr $r4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.for.cond.cleanup6:
+ ; CHECK-NEXT: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8
@@ -763,88 +785,106 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test3
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
- ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
- ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
- ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.1.vector.ph:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg
- ; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg
- ; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4
- ; CHECK: bb.2.vector.body:
- ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
- ; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv117119, align 4)
- ; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv120122, align 4)
- ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv123125, align 4)
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
- ; CHECK: bb.3.for.cond4.preheader:
- ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.4.vector.ph66:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $r9 = tMOVr $r2, 14 /* CC::al */, $noreg
- ; CHECK: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg
- ; CHECK: $r6 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r5
- ; CHECK: bb.5.vector.body65:
- ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r9, $r10
- ; CHECK: renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv108110, align 4)
- ; CHECK: renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv111113, align 4)
- ; CHECK: renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv114116, align 4)
- ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv114116, align 4)
- ; CHECK: $r10 = tMOVr $r6, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
- ; CHECK: bb.6.for.cond15.preheader:
- ; CHECK: successors: %bb.9(0x30000000), %bb.7(0x50000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: tCBZ $r3, %bb.9
- ; CHECK: bb.7.vector.ph85:
- ; CHECK: successors: %bb.8(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: $r5 = tMOVr $r0, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
- ; CHECK: bb.8.vector.body84:
- ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r5
- ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv101, align 4)
- ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv102104, align 4)
- ; CHECK: renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv105107, align 4)
- ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv105107, align 4)
- ; CHECK: $r0 = tMOVr $r5, 14 /* CC::al */, $noreg
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.8
- ; CHECK: bb.9.for.cond.cleanup17:
- ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
+ ; CHECK-NEXT: successors: %bb.9(0x30000000), %bb.1(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -20
+ ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
+ ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -28
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -32
+ ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.vector.ph:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.vector.body:
+ ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv117119, align 4)
+ ; CHECK-NEXT: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv120122, align 4)
+ ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv123125, align 4)
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.for.cond4.preheader:
+ ; CHECK-NEXT: successors: %bb.6(0x30000000), %bb.4(0x50000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.vector.ph66:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r9 = tMOVr $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r6 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.vector.body65:
+ ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r9, $r10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv108110, align 4)
+ ; CHECK-NEXT: renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv111113, align 4)
+ ; CHECK-NEXT: renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv114116, align 4)
+ ; CHECK-NEXT: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv114116, align 4)
+ ; CHECK-NEXT: $r10 = tMOVr $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.for.cond15.preheader:
+ ; CHECK-NEXT: successors: %bb.9(0x30000000), %bb.7(0x50000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: tCBZ $r3, %bb.9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.vector.ph85:
+ ; CHECK-NEXT: successors: %bb.8(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r5 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8.vector.body84:
+ ; CHECK-NEXT: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv101, align 4)
+ ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv102104, align 4)
+ ; CHECK-NEXT: renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv105107, align 4)
+ ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv105107, align 4)
+ ; CHECK-NEXT: $r0 = tMOVr $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.9.for.cond.cleanup17:
+ ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0.entry:
successors: %bb.9(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
index 13ba3594a22bfa..2f5d2934a41f41 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
@@ -78,35 +78,44 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: predicated_livout
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x40000000), %bb.4(0x40000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: $lr = MVE_WLSTP_16 killed renamable $r2, %bb.4
- ; CHECK: bb.1.for.body.preheader:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: liveins: $lr, $r0, $r1
- ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: bb.2.for.body:
- ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- ; CHECK: liveins: $lr, $q0, $r0, $r1, $r3
- ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_2_cast, align 1)
- ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_1_cast, align 1)
- ; CHECK: renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
- ; CHECK: renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, killed $noreg, $noreg, undef renamable $q0
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
- ; CHECK: bb.3.middle.block:
- ; CHECK: liveins: $q0
- ; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
- ; CHECK: bb.4.for.cond.cleanup:
- ; CHECK: liveins: $lr
- ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK-NEXT: $lr = MVE_WLSTP_16 killed renamable $r2, %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.for.body.preheader:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.for.body:
+ ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_2_cast, align 1)
+ ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_1_cast, align 1)
+ ; CHECK-NEXT: renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
+ ; CHECK-NEXT: renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, killed $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.middle.block:
+ ; CHECK-NEXT: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.for.cond.cleanup:
+ ; CHECK-NEXT: liveins: $r7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0.entry:
successors: %bb.1(0x40000000), %bb.4(0x40000000)
liveins: $r0, $r1, $r2, $lr, $r7
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
index 26336836c370e7..345fec361c69c9 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
@@ -140,85 +140,103 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: remove_mov_lr_chain
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
- ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.1.while.body.preheader:
- ; CHECK: successors: %bb.6(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2
- ; CHECK: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.6, 3 /* CC::lo */, killed $cpsr
- ; CHECK: bb.2.vector.memcheck:
- ; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2
- ; CHECK: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tCMPr killed renamable $r3, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: t2IT 8, 4, implicit-def $itstate
- ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate
- ; CHECK: tCMPr killed renamable $r3, renamable $r0, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
- ; CHECK: tBcc %bb.6, 8 /* CC::hi */, killed $cpsr
- ; CHECK: bb.3.vector.ph:
- ; CHECK: successors: %bb.4(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2
- ; CHECK: renamable $r4 = t2BICri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r12 = t2SUBri renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
- ; CHECK: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
- ; CHECK: bb.4.vector.body:
- ; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12
- ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep18, align 4)
- ; CHECK: $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
- ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg, $noreg :: (store (s128) into %ir.scevgep13, align 4)
- ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
- ; CHECK: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
- ; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
- ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
- ; CHECK: bb.5.middle.block:
- ; CHECK: successors: %bb.7(0x80000000)
- ; CHECK: liveins: $r2, $r3, $r4, $r7, $r12
- ; CHECK: tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
- ; CHECK: t2IT 0, 8, implicit-def $itstate
- ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate
- ; CHECK: tB %bb.7, 14 /* CC::al */, $noreg
- ; CHECK: bb.6:
- ; CHECK: successors: %bb.7(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2
- ; CHECK: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg
- ; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
- ; CHECK: $r3 = tMOVr killed $r1, 14 /* CC::al */, $noreg
- ; CHECK: bb.7.while.body.preheader19:
- ; CHECK: successors: %bb.8(0x80000000)
- ; CHECK: liveins: $lr, $r3, $r12
- ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r1 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: bb.8.while.body:
- ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1
- ; CHECK: renamable $s0 = VLDRS renamable $r1, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
- ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14 /* CC::al */, $noreg
- ; CHECK: VSTRS killed renamable $s0, renamable $r0, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep7)
- ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.8
- ; CHECK: bb.9.while.end:
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
+ ; CHECK-NEXT: successors: %bb.9(0x30000000), %bb.1(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16
+ ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.while.body.preheader:
+ ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.6, 3 /* CC::lo */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.vector.memcheck:
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.6(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tCMPr killed renamable $r3, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: t2IT 8, 4, implicit-def $itstate
+ ; CHECK-NEXT: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate
+ ; CHECK-NEXT: tCMPr killed renamable $r3, renamable $r0, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
+ ; CHECK-NEXT: tBcc %bb.6, 8 /* CC::hi */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.vector.ph:
+ ; CHECK-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r4 = t2BICri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r12 = t2SUBri renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.vector.body:
+ ; CHECK-NEXT: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep18, align 4)
+ ; CHECK-NEXT: $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg, $noreg :: (store (s128) into %ir.scevgep13, align 4)
+ ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
+ ; CHECK-NEXT: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: tB %bb.5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.middle.block:
+ ; CHECK-NEXT: successors: %bb.7(0x80000000)
+ ; CHECK-NEXT: liveins: $r2, $r3, $r4, $r7, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate
+ ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate
+ ; CHECK-NEXT: tB %bb.7, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6:
+ ; CHECK-NEXT: successors: %bb.7(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r3 = tMOVr killed $r1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.while.body.preheader19:
+ ; CHECK-NEXT: successors: %bb.8(0x80000000)
+ ; CHECK-NEXT: liveins: $lr, $r3, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r1 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8.while.body:
+ ; CHECK-NEXT: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $s0 = VLDRS renamable $r1, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
+ ; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: VSTRS killed renamable $s0, renamable $r0, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep7)
+ ; CHECK-NEXT: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.9.while.end:
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.entry:
successors: %bb.9(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r4, $r5, $r7, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
index 5966df967bb648..3627477607b06b 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
@@ -167,62 +167,71 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: skip_debug
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r6
- ; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
- ; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
- ; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
- ; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
- ; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
- ; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
- ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
- ; CHECK: renamable $r12 = t2LDRi12 renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !24 :: (load (s32) from %ir.a)
- ; CHECK: DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !25
- ; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
- ; CHECK: tCBZ $r2, %bb.4, debug-location !28
- ; CHECK: bb.1.vector.ph:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r12
- ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg, debug-location !28
- ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg, debug-location !28
- ; CHECK: renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, debug-location !28
- ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, $noreg, undef renamable $q0, debug-location !28
- ; CHECK: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14 /* CC::al */, $noreg, debug-location !28
- ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !28
- ; CHECK: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !28
- ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg, debug-location !28
- ; CHECK: bb.2.vector.body:
- ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
- ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg, debug-location !30
- ; CHECK: DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !30
- ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q1
- ; CHECK: MVE_VPST 8, implicit $vpr, debug-location !30
- ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg, debug-location !30 :: (load (s64) from %ir.lsr.iv14, align 2)
- ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg, debug-location !30
- ; CHECK: renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !30
- ; CHECK: renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !32
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !29
- ; CHECK: bb.3.middle.block:
- ; CHECK: successors: %bb.4(0x80000000)
- ; CHECK: liveins: $q0, $q1, $r0, $r3
- ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg, debug-location !30
- ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg, debug-location !32
- ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg, debug-location !28
- ; CHECK: bb.4.for.cond.cleanup:
- ; CHECK: liveins: $r0, $r12
- ; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
- ; CHECK: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !33 :: (store (s32) into %ir.a)
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34
+ ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4, $r6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
+ ; CHECK-NEXT: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
+ ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
+ ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
+ ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
+ ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16
+ ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
+ ; CHECK-NEXT: renamable $r12 = t2LDRi12 renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !24 :: (load (s32) from %ir.a)
+ ; CHECK-NEXT: DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !25
+ ; CHECK-NEXT: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
+ ; CHECK-NEXT: tCBZ $r2, %bb.4, debug-location !28
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.vector.ph:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg, debug-location !28
+ ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg, debug-location !28
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, debug-location !28
+ ; CHECK-NEXT: renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, $noreg, undef renamable $q0, debug-location !28
+ ; CHECK-NEXT: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14 /* CC::al */, $noreg, debug-location !28
+ ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !28
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !28
+ ; CHECK-NEXT: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg, debug-location !28
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.vector.body:
+ ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg, debug-location !30
+ ; CHECK-NEXT: DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !30
+ ; CHECK-NEXT: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q1
+ ; CHECK-NEXT: MVE_VPST 8, implicit $vpr, debug-location !30
+ ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg, debug-location !30 :: (load (s64) from %ir.lsr.iv14, align 2)
+ ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg, debug-location !30
+ ; CHECK-NEXT: renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !30
+ ; CHECK-NEXT: renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !32
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !29
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.middle.block:
+ ; CHECK-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-NEXT: liveins: $q0, $q1, $r0, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg, debug-location !30
+ ; CHECK-NEXT: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg, debug-location !32
+ ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg, debug-location !28
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.for.cond.cleanup:
+ ; CHECK-NEXT: liveins: $r0, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
+ ; CHECK-NEXT: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !33 :: (store (s32) into %ir.a)
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34
bb.0.entry:
successors: %bb.4(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r4, $r6, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
index 1bfe8f9d289cdd..45dad66907fb7d 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
@@ -1,12 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
--- |
- ; ModuleID = 'skip-vpt-debug.ll'
source_filename = "skip-vpt-debug.c"
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabihf"
- ; Function Attrs: nofree norecurse nounwind optsize
define hidden void @arm_max_no_idx_f32(float* nocapture readonly %pSrc, i32 %blockSize, float* nocapture %pResult) local_unnamed_addr #0 !dbg !13 {
entry:
call void @llvm.dbg.value(metadata float* %pSrc, metadata !24, metadata !DIExpression()), !dbg !29
@@ -52,25 +50,18 @@
ret void, !dbg !46
}
- ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
declare void @llvm.dbg.value(metadata, metadata, metadata) #1
- ; Function Attrs: nofree nosync nounwind readnone willreturn
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) #2
- ; Function Attrs: argmemonly nofree nosync nounwind readonly willreturn
declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) #3
- ; Function Attrs: nofree nosync nounwind readnone willreturn
declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>) #2
- ; Function Attrs: noduplicate nofree nosync nounwind willreturn
declare i32 @llvm.start.loop.iterations.i32(i32) #4
- ; Function Attrs: noduplicate nofree nosync nounwind willreturn
declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #4
- ; Function Attrs: nounwind readnone
declare <4 x i1> @llvm.arm.mve.vctp32(i32) #5
attributes #0 = { nofree norecurse nounwind optsize "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "frame-pointer"="none" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-dotprod,-fp16fml,-hwdiv-arm,-i8mm,-sb,-sha2" }
@@ -186,65 +177,77 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: arm_max_no_idx_f32
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
- ; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
- ; CHECK: tCBZ renamable $r1, %bb.4, debug-location !31
- ; CHECK: bb.1.vector.ph:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2
- ; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
- ; CHECK: renamable $q0 = MVE_VMOVimmi32 1152, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1, debug-location !31
- ; CHECK: bb.2.vector.body (align 4):
- ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- ; CHECK: liveins: $lr, $q0, $r0, $r2
- ; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
- ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg, debug-location !32 :: (load (s128) from %ir.lsr.iv12, align 4, !tbaa !34)
- ; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
- ; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr, debug-location !40
- ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q0, debug-location !40
- ; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
- ; CHECK: bb.3.middle.block:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $q0, $r2
- ; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
- ; CHECK: renamable $s4 = nnan ninf nsz VFP_VMAXNMS renamable $s2, renamable $s3, debug-location !31
- ; CHECK: renamable $s0 = nnan ninf nsz VFP_VMAXNMS killed renamable $s0, killed renamable $s1, implicit killed $q0, debug-location !31
- ; CHECK: renamable $s0 = nnan ninf nsz VFP_VMAXNMS killed renamable $s0, killed renamable $s4, debug-location !31
- ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
- ; CHECK: bb.4:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $r2
- ; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
- ; CHECK: renamable $s0 = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)
- ; CHECK: bb.5.while.end:
- ; CHECK: liveins: $r2, $s0
- ; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
- ; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
- ; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg, debug-location !45 :: (store (s32) into %ir.pResult, !tbaa !34)
- ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, debug-location !46
- ; CHECK: bb.6 (align 4):
- ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
+ ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: tCBZ renamable $r1, %bb.4, debug-location !31
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.vector.ph:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 1152, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1, debug-location !31
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.vector.body (align 4):
+ ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg, debug-location !32 :: (load (s128) from %ir.lsr.iv12, align 4, !tbaa !34)
+ ; CHECK-NEXT: DBG_VALUE $r0, $noreg, !24, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
+ ; CHECK-NEXT: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr, debug-location !40
+ ; CHECK-NEXT: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q0, debug-location !40
+ ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !25, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.middle.block:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $q0, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: renamable $s4 = nnan ninf nsz VFP_VMAXNMS renamable $s2, renamable $s3, debug-location !31
+ ; CHECK-NEXT: renamable $s0 = nnan ninf nsz VFP_VMAXNMS killed renamable $s0, killed renamable $s1, implicit killed $q0, debug-location !31
+ ; CHECK-NEXT: renamable $s0 = nnan ninf nsz VFP_VMAXNMS killed renamable $s0, killed renamable $s4, debug-location !31
+ ; CHECK-NEXT: tB %bb.5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: renamable $s0 = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.while.end:
+ ; CHECK-NEXT: liveins: $r2, $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
+ ; CHECK-NEXT: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg, debug-location !45 :: (store (s32) into %ir.pResult, !tbaa !34)
+ ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, debug-location !46
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6 (align 4):
+ ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 4
bb.0.entry:
successors: %bb.4(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r7, $lr
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir
index 1bd1d6b99e4225..c42316b0bf6a97 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir
@@ -25,7 +25,7 @@ body: |
; CHECK-LABEL: name: none
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.5(0x5c0b8170), %bb.1(0x23f47e90)
- ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r4, $r5, $r6, $lr
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
@@ -42,7 +42,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
- ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r6, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r3 = t2LDRHi12 $sp, 16, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tLSLri killed renamable $r1, 1, 14 /* CC::al */, $noreg
@@ -156,7 +156,7 @@ body: |
; CHECK-LABEL: name: copyin
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.5(0x5c0b8170), %bb.1(0x23f47e90)
- ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r4, $r5, $r6, $lr
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
@@ -173,7 +173,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
- ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r6, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r3 = t2LDRHi12 $sp, 16, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tLSLri killed renamable $r1, 1, 14 /* CC::al */, $noreg
@@ -289,7 +289,7 @@ body: |
; CHECK-LABEL: name: copyout
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.5(0x5c0b8170), %bb.1(0x23f47e90)
- ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r4, $r5, $r6, $lr
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
@@ -306,7 +306,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
- ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r6, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r3 = t2LDRHi12 $sp, 16, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tLSLri killed renamable $r1, 1, 14 /* CC::al */, $noreg
@@ -336,7 +336,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.2(0x7c000000)
- ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3, $r6, $r12
+ ; CHECK-NEXT: liveins: $d0, $d1, $r0, $r1, $r2, $r3, $r6, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r3, dead $cpsr = nuw nsw tADDi8 killed renamable $r3, 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r0 = tADDhirr killed renamable $r0, renamable $r1, 14 /* CC::al */, $noreg
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
index 7e2eda863d5dac..7abe42b6522661 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
@@ -231,136 +231,160 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: unrolled_and_vector
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.11(0x30000000), %bb.1(0x50000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r11
- ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
- ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
- ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
- ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
- ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r11
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -24
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
- ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
- ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.1.vector.memcheck:
- ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: tCMPr renamable $r4, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r12 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
- ; CHECK: tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r6 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
- ; CHECK: tCMPr killed renamable $r4, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r4 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
- ; CHECK: tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
- ; CHECK: renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
- ; CHECK: dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14 /* CC::al */, $noreg
- ; CHECK: t2IT 0, 4, implicit-def $itstate
- ; CHECK: renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0 /* CC::eq */, $cpsr, $noreg, implicit killed $r6, implicit $itstate
- ; CHECK: dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0 /* CC::eq */, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate
- ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.2.for.body.preheader:
- ; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
- ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r12 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.6, 2 /* CC::hs */, killed $cpsr
- ; CHECK: bb.3:
- ; CHECK: successors: %bb.8(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r12
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: tB %bb.8, 14 /* CC::al */, $noreg
- ; CHECK: bb.4.vector.ph:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: $lr = MVE_DLSTP_8 killed renamable $r3
- ; CHECK: bb.5.vector.body:
- ; CHECK: successors: %bb.5(0x7c000000), %bb.11(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2
- ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv46, align 1)
- ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv4749, align 1)
- ; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
- ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5052, align 1)
- ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
- ; CHECK: tB %bb.11, 14 /* CC::al */, $noreg
- ; CHECK: bb.6.for.body.preheader.new:
- ; CHECK: successors: %bb.7(0x80000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
- ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: bb.7.for.body:
- ; CHECK: successors: %bb.7(0x7c000000), %bb.8(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
- ; CHECK: renamable $r4 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep2453)
- ; CHECK: renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep2854)
- ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
- ; CHECK: tSTRBr killed renamable $r4, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep3255)
- ; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep40)
- ; CHECK: renamable $r5 = tLDRBi renamable $r6, 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep42)
- ; CHECK: renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
- ; CHECK: t2STRBi12 killed renamable $r8, renamable $r5, 1, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep44)
- ; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 2, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep34)
- ; CHECK: renamable $r4 = tLDRBi renamable $r6, 2, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep36)
- ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14 /* CC::al */, $noreg
- ; CHECK: tSTRBi killed renamable $r4, renamable $r5, 2, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep38)
- ; CHECK: renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep22)
- ; CHECK: renamable $r6 = tLDRBi killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep26)
- ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg
- ; CHECK: tSTRBi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep30)
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.7
- ; CHECK: bb.8.for.cond.cleanup.loopexit.unr-lcssa:
- ; CHECK: successors: %bb.11(0x30000000), %bb.9(0x50000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
- ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.9.for.body.epil:
- ; CHECK: successors: %bb.11(0x40000000), %bb.10(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
- ; CHECK: renamable $r6 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil)
- ; CHECK: t2CMPri renamable $r12, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil)
- ; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14 /* CC::al */, $noreg
- ; CHECK: tSTRBr killed renamable $r6, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil)
- ; CHECK: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
- ; CHECK: bb.10.for.body.epil.1:
- ; CHECK: successors: %bb.11(0x40000000), %bb.12(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
- ; CHECK: renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: t2CMPri killed renamable $r12, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: renamable $r5 = tLDRBr renamable $r1, $r6, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil.1)
- ; CHECK: renamable $r4 = tLDRBr renamable $r2, $r6, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil.1)
- ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
- ; CHECK: tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil.1)
- ; CHECK: tBcc %bb.12, 1 /* CC::ne */, killed $cpsr
- ; CHECK: bb.11.for.cond.cleanup:
- ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
- ; CHECK: bb.12.for.body.epil.2:
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r1 = tLDRBr killed renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil.2)
- ; CHECK: renamable $r2 = tLDRBr killed renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil.2)
- ; CHECK: renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
- ; CHECK: tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil.2)
- ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11
- ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
+ ; CHECK-NEXT: successors: %bb.11(0x30000000), %bb.1(0x50000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -16
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -20
+ ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
+ ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r11
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -24
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -28
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -32
+ ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.vector.memcheck:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tCMPr renamable $r4, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r12 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
+ ; CHECK-NEXT: tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r6 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
+ ; CHECK-NEXT: tCMPr killed renamable $r4, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r4 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
+ ; CHECK-NEXT: tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate
+ ; CHECK-NEXT: renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0 /* CC::eq */, $cpsr, $noreg, implicit killed $r6, implicit $itstate
+ ; CHECK-NEXT: dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0 /* CC::eq */, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate
+ ; CHECK-NEXT: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.for.body.preheader:
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.6(0x40000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r12 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.6, 2 /* CC::hs */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: successors: %bb.8(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tB %bb.8, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.vector.ph:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $lr = MVE_DLSTP_8 killed renamable $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.vector.body:
+ ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.11(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv46, align 1)
+ ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv4749, align 1)
+ ; CHECK-NEXT: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
+ ; CHECK-NEXT: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5052, align 1)
+ ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.5
+ ; CHECK-NEXT: tB %bb.11, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.for.body.preheader.new:
+ ; CHECK-NEXT: successors: %bb.7(0x80000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.for.body:
+ ; CHECK-NEXT: successors: %bb.7(0x7c000000), %bb.8(0x04000000)
+ ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r4 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep2453)
+ ; CHECK-NEXT: renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep2854)
+ ; CHECK-NEXT: renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRBr killed renamable $r4, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep3255)
+ ; CHECK-NEXT: renamable $r8 = t2LDRBi12 renamable $r9, 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep40)
+ ; CHECK-NEXT: renamable $r5 = tLDRBi renamable $r6, 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep42)
+ ; CHECK-NEXT: renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRBi12 killed renamable $r8, renamable $r5, 1, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep44)
+ ; CHECK-NEXT: renamable $r8 = t2LDRBi12 renamable $r9, 2, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep34)
+ ; CHECK-NEXT: renamable $r4 = tLDRBi renamable $r6, 2, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep36)
+ ; CHECK-NEXT: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRBi killed renamable $r4, renamable $r5, 2, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep38)
+ ; CHECK-NEXT: renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep22)
+ ; CHECK-NEXT: renamable $r6 = tLDRBi killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep26)
+ ; CHECK-NEXT: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRBi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep30)
+ ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8.for.cond.cleanup.loopexit.unr-lcssa:
+ ; CHECK-NEXT: successors: %bb.11(0x30000000), %bb.9(0x50000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.9.for.body.epil:
+ ; CHECK-NEXT: successors: %bb.11(0x40000000), %bb.10(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r6 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil)
+ ; CHECK-NEXT: t2CMPri renamable $r12, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil)
+ ; CHECK-NEXT: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRBr killed renamable $r6, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil)
+ ; CHECK-NEXT: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.10.for.body.epil.1:
+ ; CHECK-NEXT: successors: %bb.11(0x40000000), %bb.12(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2CMPri killed renamable $r12, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: renamable $r5 = tLDRBr renamable $r1, $r6, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil.1)
+ ; CHECK-NEXT: renamable $r4 = tLDRBr renamable $r2, $r6, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil.1)
+ ; CHECK-NEXT: renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil.1)
+ ; CHECK-NEXT: tBcc %bb.12, 1 /* CC::ne */, killed $cpsr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.11.for.cond.cleanup:
+ ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.12.for.body.epil.2:
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: renamable $r1 = tLDRBr killed renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil.2)
+ ; CHECK-NEXT: renamable $r2 = tLDRBr killed renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil.2)
+ ; CHECK-NEXT: renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil.2)
+ ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11
+ ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0.entry:
successors: %bb.11(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r11
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