[llvm] [AMDGPU] Speed up SIRegisterInfo::getReservedRegs (PR #79610)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 26 08:39:29 PST 2024
================
@@ -693,20 +699,29 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
}
}
- for (unsigned i = MaxNumVGPRs; i < TotalNumVGPRs; ++i) {
- unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
- reserveRegisterTuples(Reserved, Reg);
+ for (const TargetRegisterClass *RC : regclasses()) {
+ if (RC->isBaseClass() && isVGPRClass(RC)) {
+ unsigned NumRegs = divideCeil(getRegSizeInBits(*RC), 32);
+ for (MCPhysReg Reg : *RC) {
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arsenm wrote:
I don't know if it's formally guaranteed, but with the way it's generated it always will be in order
https://github.com/llvm/llvm-project/pull/79610
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