[llvm] f13aac6 - [RISCV] Add TuneNoSinkSplatOperands to sifive-p670 (#79492)

[via llvm-commits]

Author: Michael Maitland
Date: 2024-01-26T11:05:04-05:00
New Revision: f13aac6517532bd1ec016d432c23e92ab6450313

URL: https://github.com/llvm/llvm-project/commit/f13aac6517532bd1ec016d432c23e92ab6450313
DIFF: https://github.com/llvm/llvm-project/commit/f13aac6517532bd1ec016d432c23e92ab6450313.diff

LOG: [RISCV] Add TuneNoSinkSplatOperands to sifive-p670 (#79492)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVProcessors.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 03ca505d100df4f..59bb811058d4886 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -280,7 +280,8 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
                                       [TuneNoDefaultUnroll,
                                        TuneConditionalCompressedMoveFusion,
                                        TuneLUIADDIFusion,
-                                       TuneAUIPCADDIFusion]>;
+                                       TuneAUIPCADDIFusion,
+                                       TuneNoSinkSplatOperands]>;
 
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
                                               SyntacoreSCR1Model,