[llvm] 035f33b - [X86][CodeGen] Add NDD entries for X86InstrInfo::foldImmediate

[Shengchen Kan via llvm-commits]

Author: Shengchen Kan
Date: 2024-01-26T22:11:57+08:00
New Revision: 035f33bf4138ac7b7360a83438988ce80bda5098

URL: https://github.com/llvm/llvm-project/commit/035f33bf4138ac7b7360a83438988ce80bda5098
DIFF: https://github.com/llvm/llvm-project/commit/035f33bf4138ac7b7360a83438988ce80bda5098.diff

LOG: [X86][CodeGen] Add NDD entries for X86InstrInfo::foldImmediate

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstrInfo.cpp
    llvm/test/CodeGen/X86/select_const_i128.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 21ea4257114c4e6..6f08ed74d7ec61b 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -5488,14 +5488,14 @@ static bool canConvert2Copy(unsigned Opc) {
   switch (Opc) {
   default:
     return false;
-  case X86::ADD64ri32:
-  case X86::SUB64ri32:
-  case X86::OR64ri32:
-  case X86::XOR64ri32:
-  case X86::ADD32ri:
-  case X86::SUB32ri:
-  case X86::OR32ri:
-  case X86::XOR32ri:
+  CASE_ND(ADD64ri32)
+  CASE_ND(SUB64ri32)
+  CASE_ND(OR64ri32)
+  CASE_ND(XOR64ri32)
+  CASE_ND(ADD32ri)
+  CASE_ND(SUB32ri)
+  CASE_ND(OR32ri)
+  CASE_ND(XOR32ri)
     return true;
   }
 }
@@ -5508,7 +5508,9 @@ static unsigned convertALUrr2ALUri(unsigned Opc) {
     return 0;
 #define FROM_TO(FROM, TO)                                                      \
   case X86::FROM:                                                              \
-    return X86::TO;
+    return X86::TO;                                                            \
+  case X86::FROM##_ND:                                                         \
+    return X86::TO##_ND;
     FROM_TO(ADD64rr, ADD64ri32)
     FROM_TO(ADC64rr, ADC64ri32)
     FROM_TO(SUB64rr, SUB64ri32)
@@ -5516,8 +5518,6 @@ static unsigned convertALUrr2ALUri(unsigned Opc) {
     FROM_TO(AND64rr, AND64ri32)
     FROM_TO(OR64rr, OR64ri32)
     FROM_TO(XOR64rr, XOR64ri32)
-    FROM_TO(TEST64rr, TEST64ri32)
-    FROM_TO(CMP64rr, CMP64ri32)
     FROM_TO(SHR64rCL, SHR64ri)
     FROM_TO(SHL64rCL, SHL64ri)
     FROM_TO(SAR64rCL, SAR64ri)
@@ -5532,8 +5532,6 @@ static unsigned convertALUrr2ALUri(unsigned Opc) {
     FROM_TO(AND32rr, AND32ri)
     FROM_TO(OR32rr, OR32ri)
     FROM_TO(XOR32rr, XOR32ri)
-    FROM_TO(TEST32rr, TEST32ri)
-    FROM_TO(CMP32rr, CMP32ri)
     FROM_TO(SHR32rCL, SHR32ri)
     FROM_TO(SHL32rCL, SHL32ri)
     FROM_TO(SAR32rCL, SAR32ri)
@@ -5541,6 +5539,14 @@ static unsigned convertALUrr2ALUri(unsigned Opc) {
     FROM_TO(ROR32rCL, ROR32ri)
     FROM_TO(RCL32rCL, RCL32ri)
     FROM_TO(RCR32rCL, RCR32ri)
+#undef FROM_TO
+#define FROM_TO(FROM, TO)                                                      \
+  case X86::FROM:                                                              \
+    return X86::TO;
+    FROM_TO(TEST64rr, TEST64ri32)
+    FROM_TO(CMP64rr, CMP64ri32)
+    FROM_TO(TEST32rr, TEST32ri)
+    FROM_TO(CMP32rr, CMP32ri)
 #undef FROM_TO
   }
 }
@@ -5634,7 +5640,9 @@ bool X86InstrInfo::foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
 
   // For SUB instructions the immediate can only be the second source operand.
   if ((NewOpc == X86::SUB64ri32 || NewOpc == X86::SUB32ri ||
-       NewOpc == X86::SBB64ri32 || NewOpc == X86::SBB32ri) &&
+       NewOpc == X86::SBB64ri32 || NewOpc == X86::SBB32ri ||
+       NewOpc == X86::SUB64ri32_ND || NewOpc == X86::SUB32ri_ND ||
+       NewOpc == X86::SBB64ri32_ND || NewOpc == X86::SBB32ri_ND) &&
       UseMI.findRegisterUseOperandIdx(Reg) != 2)
     return false;
   // For CMP instructions the immediate can only be at index 1.

diff  --git a/llvm/test/CodeGen/X86/select_const_i128.ll b/llvm/test/CodeGen/X86/select_const_i128.ll
index 503cf13ec413157..d7859baec815c14 100644
--- a/llvm/test/CodeGen/X86/select_const_i128.ll
+++ b/llvm/test/CodeGen/X86/select_const_i128.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 -mattr=+ndd | FileCheck --check-prefix=NDD %s
 
 define i128 @select_eq_i128(ptr %a) {
 ; CHECK-LABEL: select_eq_i128:
@@ -13,6 +14,18 @@ define i128 @select_eq_i128(ptr %a) {
 ; CHECK-NEXT:    movabsq $9223372036854775807, %rdx # imm = 0x7FFFFFFFFFFFFFFF
 ; CHECK-NEXT:    adcq $0, %rdx
 ; CHECK-NEXT:    retq
+;
+; NDD-LABEL: select_eq_i128:
+; NDD:       # %bb.0:
+; NDD-NEXT:    movdqa (%rdi), %xmm0
+; NDD-NEXT:    pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; NDD-NEXT:    xorl %eax, %eax
+; NDD-NEXT:    ptest %xmm0, %xmm0
+; NDD-NEXT:    setne %al
+; NDD-NEXT:    addq $-1, %rax
+; NDD-NEXT:    movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; NDD-NEXT:    adcq $0, %rcx, %rdx
+; NDD-NEXT:    retq
   %1 = load i128, ptr %a, align 16
   %cmp = icmp eq i128 %1, 1
   %cond = select i1 %cmp, i128 170141183460469231731687303715884105727, i128 -170141183460469231731687303715884105728