[llvm] [AArch64][GlobalISel] Lower Shuffle Vector to REV (PR #79591)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff bfef161a80b62723bedad996aa7a697f99e6802a ba6e25f7174c02cf86cee18f3679cf1be83cae89 -- llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index f5e0cb20e7..9bc5815ae0 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -244,7 +244,7 @@ bool matchREV(MachineInstr &MI, MachineRegisterInfo &MRI,
 
   // Try to produce a G_REV instruction
   for (unsigned LaneSize : {64U, 32U, 16U}) {
-    if (isREVMask(ShuffleMask, EltSize, NumElts, LaneSize)){
+    if (isREVMask(ShuffleMask, EltSize, NumElts, LaneSize)) {
       unsigned Opcode;
       if (LaneSize == 64U)
         Opcode = AArch64::G_REV64;

``````````

</details>


https://github.com/llvm/llvm-project/pull/79591