[llvm] 550f0eb - [NFC] Rename TargetInstrInfo::FoldImmediate to TargetInstrInfo::foldImmediate and simplify implementation for X86
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 26 04:51:42 PST 2024
Author: Shengchen Kan
Date: 2024-01-26T20:50:58+08:00
New Revision: 550f0eb2ce12435b696b6c2a5fcbede8f6db68b1
URL: https://github.com/llvm/llvm-project/commit/550f0eb2ce12435b696b6c2a5fcbede8f6db68b1
DIFF: https://github.com/llvm/llvm-project/commit/550f0eb2ce12435b696b6c2a5fcbede8f6db68b1.diff
LOG: [NFC] Rename TargetInstrInfo::FoldImmediate to TargetInstrInfo::foldImmediate and simplify implementation for X86
Added:
Modified:
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/CodeGen/PeepholeOptimizer.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.h
llvm/lib/Target/VE/VEInstrInfo.cpp
llvm/lib/Target/VE/VEInstrInfo.h
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index a113100f04e621..30c51b58a291c9 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1710,7 +1710,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// then the caller may assume that DefMI has been erased from its parent
/// block. The caller may assume that it will not be erased by this
/// function otherwise.
- virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
+ virtual bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
Register Reg, MachineRegisterInfo *MRI) const {
return false;
}
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 76b3b16af16bdc..1b1f22e827cb1e 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -1428,9 +1428,9 @@ bool PeepholeOptimizer::foldImmediate(
continue;
DenseMap<Register, MachineInstr *>::iterator II = ImmDefMIs.find(Reg);
assert(II != ImmDefMIs.end() && "couldn't find immediate definition");
- if (TII->FoldImmediate(MI, *II->second, Reg, MRI)) {
+ if (TII->foldImmediate(MI, *II->second, Reg, MRI)) {
++NumImmFold;
- // FoldImmediate can delete ImmDefMI if MI was its only user. If ImmDefMI
+ // foldImmediate can delete ImmDefMI if MI was its only user. If ImmDefMI
// is not deleted, and we happened to get a same MI, we can delete MI and
// replace its users.
if (MRI->getVRegDef(Reg) &&
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f4ca27808a3041..696e74cb592f93 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3351,7 +3351,7 @@ void SIInstrInfo::removeModOperands(MachineInstr &MI) const {
}
}
-bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
+bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
Register Reg, MachineRegisterInfo *MRI) const {
if (!MRI->hasOneNonDBGUse(Reg))
return false;
@@ -6126,7 +6126,7 @@ void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,
// Try to eliminate the copy if it is copying an immediate value.
if (Def->isMoveImmediate() && DstRC != &AMDGPU::VReg_1RegClass)
- FoldImmediate(*Copy, *Def, OpReg, &MRI);
+ foldImmediate(*Copy, *Def, OpReg, &MRI);
bool ImpDef = Def->isImplicitDef();
while (!ImpDef && Def && Def->isCopy()) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 1c9dacc09f8154..eaee90dd3bd2d8 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -393,7 +393,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
void removeModOperands(MachineInstr &MI) const;
- bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
+ bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
MachineRegisterInfo *MRI) const final;
unsigned getMachineCSELookAheadLimit() const override { return 500; }
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 4bf65be6f10262..e723c085802cd7 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -3308,7 +3308,7 @@ bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const {
return true;
}
-bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
+bool ARMBaseInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
Register Reg,
MachineRegisterInfo *MRI) const {
// Fold large immediates into add, sub, or, xor.
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 6aebf3b64e8d43..11800d82d5f44b 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -308,9 +308,9 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
SmallPtrSetImpl<MachineInstr *> &SeenMIs,
bool) const override;
- /// FoldImmediate - 'Reg' is known to be defined by a move immediate
+ /// foldImmediate - 'Reg' is known to be defined by a move immediate
/// instruction, try to fold the immediate into the use instruction.
- bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
+ bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
MachineRegisterInfo *MRI) const override;
unsigned getNumMicroOps(const InstrItineraryData *ItinData,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 15f6b65dea83c4..9c5968c773c740 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2100,7 +2100,7 @@ bool PPCInstrInfo::onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
// Folds zero into instructions which have a load immediate zero as an operand
// but also recognize zero as immediate zero. If the definition of the load
// has no more users it is deleted.
-bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
+bool PPCInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
Register Reg, MachineRegisterInfo *MRI) const {
bool Changed = onlyFoldImmediate(UseMI, DefMI, Reg);
if (MRI->use_nodbg_empty(Reg))
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 75f9cd1c206d82..ae8cb89daad37c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -480,7 +480,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
- bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
+ bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
MachineRegisterInfo *MRI) const override;
bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7d913a77cc7155..0f450a4bf9692b 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -168,7 +168,7 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
const TargetRegisterClass *
PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
const {
- // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
+ // Note that PPCInstrInfo::foldImmediate also directly uses this Kind value
// when it checks for ZERO folding.
if (Kind == 1) {
if (TM.isPPC64())
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index bf6547cc87ec5e..a2cea31cd4cfaf 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -610,7 +610,7 @@ void SystemZInstrInfo::insertSelect(MachineBasicBlock &MBB,
.addImm(CCValid).addImm(CCMask);
}
-bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
+bool SystemZInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
Register Reg,
MachineRegisterInfo *MRI) const {
unsigned DefOpc = DefMI.getOpcode();
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index bb883ea464d376..3aa533590c3619 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -254,7 +254,7 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
const DebugLoc &DL, Register DstReg,
ArrayRef<MachineOperand> Cond, Register TrueReg,
Register FalseReg) const override;
- bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
+ bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
MachineRegisterInfo *MRI) const override;
bool isPredicable(const MachineInstr &MI) const override;
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp
index ebb9e21389c37b..c7e6332151c78d 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.cpp
+++ b/llvm/lib/Target/VE/VEInstrInfo.cpp
@@ -575,9 +575,9 @@ void VEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
report_fatal_error("Can't load this register from stack slot");
}
-bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
+bool VEInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
Register Reg, MachineRegisterInfo *MRI) const {
- LLVM_DEBUG(dbgs() << "FoldImmediate\n");
+ LLVM_DEBUG(dbgs() << "foldImmediate\n");
LLVM_DEBUG(dbgs() << "checking DefMI\n");
int64_t ImmVal;
diff --git a/llvm/lib/Target/VE/VEInstrInfo.h b/llvm/lib/Target/VE/VEInstrInfo.h
index 4fe56f24116f8c..8f4d031ed7edde 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.h
+++ b/llvm/lib/Target/VE/VEInstrInfo.h
@@ -104,7 +104,7 @@ class VEInstrInfo : public VEGenInstrInfo {
/// Optimization {
- bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
+ bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
MachineRegisterInfo *MRI) const override;
/// } Optimization
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index dfd3d888870861..21ea4257114c4e 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -5483,153 +5483,78 @@ MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
return nullptr;
}
+/// \returns true if the instruction can be changed to COPY when imm is 0.
+static bool canConvert2Copy(unsigned Opc) {
+ switch (Opc) {
+ default:
+ return false;
+ case X86::ADD64ri32:
+ case X86::SUB64ri32:
+ case X86::OR64ri32:
+ case X86::XOR64ri32:
+ case X86::ADD32ri:
+ case X86::SUB32ri:
+ case X86::OR32ri:
+ case X86::XOR32ri:
+ return true;
+ }
+}
+
/// Convert an ALUrr opcode to corresponding ALUri opcode. Such as
/// ADD32rr ==> ADD32ri
-/// ShiftRotate will be set to true if the Opcode is shift or rotate.
-/// If the ALUri can be further changed to COPY when the immediate is 0, set
-/// CanConvert2Copy to true.
-static unsigned ConvertALUrr2ALUri(unsigned Opcode, bool &CanConvert2Copy,
- bool &ShiftRotate) {
- CanConvert2Copy = false;
- ShiftRotate = false;
- unsigned NewOpcode = 0;
- switch (Opcode) {
- case X86::ADD64rr:
- NewOpcode = X86::ADD64ri32;
- CanConvert2Copy = true;
- break;
- case X86::ADC64rr:
- NewOpcode = X86::ADC64ri32;
- break;
- case X86::SUB64rr:
- NewOpcode = X86::SUB64ri32;
- CanConvert2Copy = true;
- break;
- case X86::SBB64rr:
- NewOpcode = X86::SBB64ri32;
- break;
- case X86::AND64rr:
- NewOpcode = X86::AND64ri32;
- break;
- case X86::OR64rr:
- NewOpcode = X86::OR64ri32;
- CanConvert2Copy = true;
- break;
- case X86::XOR64rr:
- NewOpcode = X86::XOR64ri32;
- CanConvert2Copy = true;
- break;
- case X86::TEST64rr:
- NewOpcode = X86::TEST64ri32;
- break;
- case X86::CMP64rr:
- NewOpcode = X86::CMP64ri32;
- break;
- case X86::SHR64rCL:
- NewOpcode = X86::SHR64ri;
- ShiftRotate = true;
- break;
- case X86::SHL64rCL:
- NewOpcode = X86::SHL64ri;
- ShiftRotate = true;
- break;
- case X86::SAR64rCL:
- NewOpcode = X86::SAR64ri;
- ShiftRotate = true;
- break;
- case X86::ROL64rCL:
- NewOpcode = X86::ROL64ri;
- ShiftRotate = true;
- break;
- case X86::ROR64rCL:
- NewOpcode = X86::ROR64ri;
- ShiftRotate = true;
- break;
- case X86::RCL64rCL:
- NewOpcode = X86::RCL64ri;
- ShiftRotate = true;
- break;
- case X86::RCR64rCL:
- NewOpcode = X86::RCR64ri;
- ShiftRotate = true;
- break;
- case X86::ADD32rr:
- NewOpcode = X86::ADD32ri;
- CanConvert2Copy = true;
- break;
- case X86::ADC32rr:
- NewOpcode = X86::ADC32ri;
- break;
- case X86::SUB32rr:
- NewOpcode = X86::SUB32ri;
- CanConvert2Copy = true;
- break;
- case X86::SBB32rr:
- NewOpcode = X86::SBB32ri;
- break;
- case X86::AND32rr:
- NewOpcode = X86::AND32ri;
- break;
- case X86::OR32rr:
- NewOpcode = X86::OR32ri;
- CanConvert2Copy = true;
- break;
- case X86::XOR32rr:
- NewOpcode = X86::XOR32ri;
- CanConvert2Copy = true;
- break;
- case X86::TEST32rr:
- NewOpcode = X86::TEST32ri;
- break;
- case X86::CMP32rr:
- NewOpcode = X86::CMP32ri;
- break;
- case X86::SHR32rCL:
- NewOpcode = X86::SHR32ri;
- ShiftRotate = true;
- break;
- case X86::SHL32rCL:
- NewOpcode = X86::SHL32ri;
- ShiftRotate = true;
- break;
- case X86::SAR32rCL:
- NewOpcode = X86::SAR32ri;
- ShiftRotate = true;
- break;
- case X86::ROL32rCL:
- NewOpcode = X86::ROL32ri;
- ShiftRotate = true;
- break;
- case X86::ROR32rCL:
- NewOpcode = X86::ROR32ri;
- ShiftRotate = true;
- break;
- case X86::RCL32rCL:
- NewOpcode = X86::RCL32ri;
- ShiftRotate = true;
- break;
- case X86::RCR32rCL:
- NewOpcode = X86::RCR32ri;
- ShiftRotate = true;
- break;
+static unsigned convertALUrr2ALUri(unsigned Opc) {
+ switch (Opc) {
+ default:
+ return 0;
+#define FROM_TO(FROM, TO) \
+ case X86::FROM: \
+ return X86::TO;
+ FROM_TO(ADD64rr, ADD64ri32)
+ FROM_TO(ADC64rr, ADC64ri32)
+ FROM_TO(SUB64rr, SUB64ri32)
+ FROM_TO(SBB64rr, SBB64ri32)
+ FROM_TO(AND64rr, AND64ri32)
+ FROM_TO(OR64rr, OR64ri32)
+ FROM_TO(XOR64rr, XOR64ri32)
+ FROM_TO(TEST64rr, TEST64ri32)
+ FROM_TO(CMP64rr, CMP64ri32)
+ FROM_TO(SHR64rCL, SHR64ri)
+ FROM_TO(SHL64rCL, SHL64ri)
+ FROM_TO(SAR64rCL, SAR64ri)
+ FROM_TO(ROL64rCL, ROL64ri)
+ FROM_TO(ROR64rCL, ROR64ri)
+ FROM_TO(RCL64rCL, RCL64ri)
+ FROM_TO(RCR64rCL, RCR64ri)
+ FROM_TO(ADD32rr, ADD32ri)
+ FROM_TO(ADC32rr, ADC32ri)
+ FROM_TO(SUB32rr, SUB32ri)
+ FROM_TO(SBB32rr, SBB32ri)
+ FROM_TO(AND32rr, AND32ri)
+ FROM_TO(OR32rr, OR32ri)
+ FROM_TO(XOR32rr, XOR32ri)
+ FROM_TO(TEST32rr, TEST32ri)
+ FROM_TO(CMP32rr, CMP32ri)
+ FROM_TO(SHR32rCL, SHR32ri)
+ FROM_TO(SHL32rCL, SHL32ri)
+ FROM_TO(SAR32rCL, SAR32ri)
+ FROM_TO(ROL32rCL, ROL32ri)
+ FROM_TO(ROR32rCL, ROR32ri)
+ FROM_TO(RCL32rCL, RCL32ri)
+ FROM_TO(RCR32rCL, RCR32ri)
+#undef FROM_TO
}
- return NewOpcode;
}
-/// Real implementation of FoldImmediate.
/// Reg is assigned ImmVal in DefMI, and is used in UseMI.
/// If MakeChange is true, this function tries to replace Reg by ImmVal in
/// UseMI. If MakeChange is false, just check if folding is possible.
-/// Return true if folding is successful or possible.
-bool X86InstrInfo::FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
+//
+/// \returns true if folding is successful or possible.
+bool X86InstrInfo::foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
Register Reg, int64_t ImmVal,
MachineRegisterInfo *MRI,
bool MakeChange) const {
bool Modified = false;
- bool ShiftRotate = false;
- // When ImmVal is 0, some instructions can be changed to COPY.
- bool CanChangeToCopy = false;
- unsigned Opc = UseMI.getOpcode();
// 64 bit operations accept sign extended 32 bit immediates.
// 32 bit operations accept all 32 bit immediates, so we don't need to check
@@ -5651,6 +5576,7 @@ bool X86InstrInfo::FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
!MRI->hasOneNonDBGUse(Reg))
return false;
+ unsigned Opc = UseMI.getOpcode();
unsigned NewOpc;
if (Opc == TargetOpcode::COPY) {
Register ToReg = UseMI.getOperand(0).getReg();
@@ -5701,7 +5627,7 @@ bool X86InstrInfo::FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
else
return false;
} else
- NewOpc = ConvertALUrr2ALUri(Opc, CanChangeToCopy, ShiftRotate);
+ NewOpc = convertALUrr2ALUri(Opc);
if (!NewOpc)
return false;
@@ -5716,7 +5642,9 @@ bool X86InstrInfo::FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
UseMI.findRegisterUseOperandIdx(Reg) != 1)
return false;
- if (ShiftRotate) {
+ using namespace X86;
+ if (isSHL(Opc) || isSHR(Opc) || isSAR(Opc) || isROL(Opc) || isROR(Opc) ||
+ isRCL(Opc) || isRCR(Opc)) {
unsigned RegIdx = UseMI.findRegisterUseOperandIdx(Reg);
if (RegIdx < 2)
return false;
@@ -5740,7 +5668,7 @@ bool X86InstrInfo::FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
if (!Modified) {
// Modify the instruction.
- if (ImmVal == 0 && CanChangeToCopy &&
+ if (ImmVal == 0 && canConvert2Copy(NewOpc) &&
UseMI.registerDefIsDead(X86::EFLAGS)) {
// %100 = add %101, 0
// ==>
@@ -5776,15 +5704,15 @@ bool X86InstrInfo::FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
return true;
}
-/// FoldImmediate - 'Reg' is known to be defined by a move immediate
+/// foldImmediate - 'Reg' is known to be defined by a move immediate
/// instruction, try to fold the immediate into the use instruction.
-bool X86InstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
+bool X86InstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
Register Reg, MachineRegisterInfo *MRI) const {
int64_t ImmVal;
if (!getConstValDefinedInReg(DefMI, Reg, ImmVal))
return false;
- return FoldImmediateImpl(UseMI, &DefMI, Reg, ImmVal, MRI, true);
+ return foldImmediateImpl(UseMI, &DefMI, Reg, ImmVal, MRI, true);
}
/// Expand a single-def pseudo instruction to a two-addr
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 939bc7daf1c7de..af98bb12c5c2fa 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -161,6 +161,10 @@ class X86InstrInfo final : public X86GenInstrInfo {
SmallVectorImpl<MachineInstr *> &CondBranches,
bool AllowModify) const;
+ bool foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg,
+ int64_t ImmVal, MachineRegisterInfo *MRI,
+ bool MakeChange) const;
+
public:
explicit X86InstrInfo(X86Subtarget &STI);
@@ -575,13 +579,9 @@ class X86InstrInfo final : public X86GenInstrInfo {
Register &FoldAsLoadDefReg,
MachineInstr *&DefMI) const override;
- bool FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg,
- int64_t ImmVal, MachineRegisterInfo *MRI,
- bool MakeChange) const;
-
/// Reg is known to be defined by a move immediate instruction, try to fold
/// the immediate into the use instruction.
- bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
+ bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
MachineRegisterInfo *MRI) const override;
std::pair<unsigned, unsigned>
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