[llvm] 8a4cb7b - [X86][test] Add MRM7r/MRM7m entries in evex format enc/dec tests

[Shengchen Kan via llvm-commits]

Author: Shengchen Kan
Date: 2024-01-26T17:22:07+08:00
New Revision: 8a4cb7b6077e51adfa87209869ab0ae83dc531a7

URL: https://github.com/llvm/llvm-project/commit/8a4cb7b6077e51adfa87209869ab0ae83dc531a7
DIFF: https://github.com/llvm/llvm-project/commit/8a4cb7b6077e51adfa87209869ab0ae83dc531a7.diff

LOG: [X86][test] Add MRM7r/MRM7m entries in evex format enc/dec tests

Added: 
    

Modified: 
    llvm/test/MC/Disassembler/X86/apx/evex-format.txt
    llvm/test/MC/X86/apx/evex-format-att.s
    llvm/test/MC/X86/apx/evex-format-intel.s

Removed: 
    


################################################################################
diff  --git a/llvm/test/MC/Disassembler/X86/apx/evex-format.txt b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt
index 88258e7e29b5c8..1c1f70b096bed9 100644
--- a/llvm/test/MC/Disassembler/X86/apx/evex-format.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt
@@ -1,4 +1,3 @@
-## NOTE: This file needs to be updated after promoted instruction is supported
 # RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
 # RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
 
@@ -98,6 +97,10 @@
 # INTEL: vpslldq	zmm0, zmmword ptr [r16 + r17], 0
 0x62,0xf9,0x79,0x48,0x73,0x3c,0x08,0x00
 
+# ATT:   sarq	$123, 291(%r16,%r17), %r18
+# INTEL: sar	r18, qword ptr [r16 + r17 + 291], 123
+0x62,0xfc,0xe8,0x10,0xc1,0xbc,0x08,0x23,0x01,0x00,0x00,0x7b
+
 ## MRMDestMem4VOp3CC
 
 # ATT:   cmpbexadd	%r18d, %r22d, 291(%r28,%r29,4)
@@ -174,6 +177,12 @@
 # INTEL: xor	r17, r16, 127
 0x62,0xfc,0xf4,0x10,0x83,0xf0,0x7f
 
+## MRM7r
+
+# ATT:   sarq	$123, %r16, %r17
+# INTEL: sar	r17, r16, 123
+0x62,0xfc,0xf4,0x10,0xc1,0xf8,0x7b
+
 ## NoCD8
 
 # ATT:   {nf}	negq	123(%r16)

diff  --git a/llvm/test/MC/X86/apx/evex-format-att.s b/llvm/test/MC/X86/apx/evex-format-att.s
index 577e196976948f..055a29fe00f32c 100644
--- a/llvm/test/MC/X86/apx/evex-format-att.s
+++ b/llvm/test/MC/X86/apx/evex-format-att.s
@@ -1,4 +1,3 @@
-## NOTE: This file needs to be updated after promoted instruction is supported
 # RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
 
 ## MRMDestMem
@@ -97,6 +96,10 @@
 # CHECK: encoding: [0x62,0xf9,0x79,0x48,0x73,0x3c,0x08,0x00]
          vpslldq	$0, (%r16,%r17), %zmm0
 
+# CHECK: sarq	$123, 291(%r16,%r17), %r18
+# CHECK: encoding: [0x62,0xfc,0xe8,0x10,0xc1,0xbc,0x08,0x23,0x01,0x00,0x00,0x7b]
+         sarq	$123, 291(%r16,%r17), %r18
+
 ## MRMDestMem4VOp3CC
 
 # CHECK: cmpbexadd	%r18d, %r22d, 291(%r28,%r29,4)
@@ -173,6 +176,12 @@
 # CHECK: encoding: [0x62,0xfc,0xf4,0x10,0x83,0xf0,0x7f]
          xorq	$127, %r16, %r17
 
+## MRM7r
+
+# CHECK: sarq	$123, %r16, %r17
+# CHECK: encoding: [0x62,0xfc,0xf4,0x10,0xc1,0xf8,0x7b]
+         sarq	$123, %r16, %r17
+
 ## NoCD8
 
 # CHECK: {nf}	negq	123(%r16)

diff  --git a/llvm/test/MC/X86/apx/evex-format-intel.s b/llvm/test/MC/X86/apx/evex-format-intel.s
index b35664343bf609..06b56078aab904 100644
--- a/llvm/test/MC/X86/apx/evex-format-intel.s
+++ b/llvm/test/MC/X86/apx/evex-format-intel.s
@@ -1,4 +1,3 @@
-## NOTE: This file needs to be updated after promoted instruction is supported
 # RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s
 
 ## MRMDestMem
@@ -97,6 +96,10 @@
 # CHECK: encoding: [0x62,0xf9,0x79,0x48,0x73,0x3c,0x08,0x00]
          vpslldq	zmm0, zmmword ptr [r16 + r17], 0
 
+# CHECK: sar	r18, qword ptr [r16 + r17 + 291], 123
+# CHECK: encoding: [0x62,0xfc,0xe8,0x10,0xc1,0xbc,0x08,0x23,0x01,0x00,0x00,0x7b]
+         sar	r18, qword ptr [r16 + r17 + 291], 123
+
 ## MRMDestMem4VOp3CC
 
 # CHECK: cmpbexadd	dword ptr [r28 + 4*r29 + 291], r22d, r18d
@@ -173,6 +176,12 @@
 # CHECK: encoding: [0x62,0xfc,0xf4,0x10,0x83,0xf0,0x7f]
          xor	r17, r16, 127
 
+## MRM7r
+
+# CHECK: sar	r17, r16, 123
+# CHECK: encoding: [0x62,0xfc,0xf4,0x10,0xc1,0xf8,0x7b]
+         sar	r17, r16, 123
+
 ## NoCD8
 
 # CHECK: {nf}	neg	qword ptr [r16 + 123]