[llvm] [X86] Support immediate encoding optimization for ndd instructions (PR #78545)

via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 26 01:14:24 PST 2024


https://github.com/XinWang10 updated https://github.com/llvm/llvm-project/pull/78545

>From a4377a9d570af1c8d78b39585048b8718e5df96b Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 17 Jan 2024 23:23:34 -0800
Subject: [PATCH 1/2] [X86] Support encoding optimization fo immediate for ndd
 instructions

---
 .../X86EncodingOptimizationForImmediate.def   | 72 +++++++++++++++++++
 llvm/test/CodeGen/X86/apx/adc.ll              | 36 +++++-----
 llvm/test/CodeGen/X86/apx/add.ll              | 16 ++---
 llvm/test/CodeGen/X86/apx/and.ll              | 14 ++--
 llvm/test/CodeGen/X86/apx/or.ll               | 16 ++---
 llvm/test/CodeGen/X86/apx/sbb.ll              | 48 ++++++-------
 llvm/test/CodeGen/X86/apx/sub.ll              | 16 ++---
 llvm/test/CodeGen/X86/apx/xor.ll              | 20 +++---
 8 files changed, 155 insertions(+), 83 deletions(-)

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def
index e475e55260ed36a..e86860e06922e6d 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def
@@ -69,4 +69,76 @@ ENTRY(IMUL64rri32, IMUL64rri8)
 ENTRY(PUSH16i, PUSH16i8)
 ENTRY(PUSH32i, PUSH32i8)
 ENTRY(PUSH64i32, PUSH64i8)
+ENTRY(ADC16mi_ND, ADC16mi8_ND)
+ENTRY(ADC16ri_ND, ADC16ri8_ND)
+ENTRY(ADC32mi_ND, ADC32mi8_ND)
+ENTRY(ADC32ri_ND, ADC32ri8_ND)
+ENTRY(ADC64mi32_ND, ADC64mi8_ND)
+ENTRY(ADC64ri32_ND, ADC64ri8_ND)
+ENTRY(SBB16mi_ND, SBB16mi8_ND)
+ENTRY(SBB16ri_ND, SBB16ri8_ND)
+ENTRY(SBB32mi_ND, SBB32mi8_ND)
+ENTRY(SBB32ri_ND, SBB32ri8_ND)
+ENTRY(SBB64mi32_ND, SBB64mi8_ND)
+ENTRY(SBB64ri32_ND, SBB64ri8_ND)
+ENTRY(ADD16mi_ND, ADD16mi8_ND)
+ENTRY(ADD16ri_ND, ADD16ri8_ND)
+ENTRY(ADD32mi_ND, ADD32mi8_ND)
+ENTRY(ADD32ri_ND, ADD32ri8_ND)
+ENTRY(ADD64mi32_ND, ADD64mi8_ND)
+ENTRY(ADD64ri32_ND, ADD64ri8_ND)
+ENTRY(AND16mi_ND, AND16mi8_ND)
+ENTRY(AND16ri_ND, AND16ri8_ND)
+ENTRY(AND32mi_ND, AND32mi8_ND)
+ENTRY(AND32ri_ND, AND32ri8_ND)
+ENTRY(AND64mi32_ND, AND64mi8_ND)
+ENTRY(AND64ri32_ND, AND64ri8_ND)
+ENTRY(OR16mi_ND, OR16mi8_ND)
+ENTRY(OR16ri_ND, OR16ri8_ND)
+ENTRY(OR32mi_ND, OR32mi8_ND)
+ENTRY(OR32ri_ND, OR32ri8_ND)
+ENTRY(OR64mi32_ND, OR64mi8_ND)
+ENTRY(OR64ri32_ND, OR64ri8_ND)
+ENTRY(SUB16mi_ND, SUB16mi8_ND)
+ENTRY(SUB16ri_ND, SUB16ri8_ND)
+ENTRY(SUB32mi_ND, SUB32mi8_ND)
+ENTRY(SUB32ri_ND, SUB32ri8_ND)
+ENTRY(SUB64mi32_ND, SUB64mi8_ND)
+ENTRY(SUB64ri32_ND, SUB64ri8_ND)
+ENTRY(XOR16mi_ND, XOR16mi8_ND)
+ENTRY(XOR16ri_ND, XOR16ri8_ND)
+ENTRY(XOR32mi_ND, XOR32mi8_ND)
+ENTRY(XOR32ri_ND, XOR32ri8_ND)
+ENTRY(XOR64mi32_ND, XOR64mi8_ND)
+ENTRY(XOR64ri32_ND, XOR64ri8_ND)
+ENTRY(ADD16mi_NF_ND, ADD16mi8_NF_ND)
+ENTRY(ADD16ri_NF_ND, ADD16ri8_NF_ND)
+ENTRY(ADD32mi_NF_ND, ADD32mi8_NF_ND)
+ENTRY(ADD32ri_NF_ND, ADD32ri8_NF_ND)
+ENTRY(ADD64mi32_NF_ND, ADD64mi8_NF_ND)
+ENTRY(ADD64ri32_NF_ND, ADD64ri8_NF_ND)
+ENTRY(AND16mi_NF_ND, AND16mi8_NF_ND)
+ENTRY(AND16ri_NF_ND, AND16ri8_NF_ND)
+ENTRY(AND32mi_NF_ND, AND32mi8_NF_ND)
+ENTRY(AND32ri_NF_ND, AND32ri8_NF_ND)
+ENTRY(AND64mi32_NF_ND, AND64mi8_NF_ND)
+ENTRY(AND64ri32_NF_ND, AND64ri8_NF_ND)
+ENTRY(OR16mi_NF_ND, OR16mi8_NF_ND)
+ENTRY(OR16ri_NF_ND, OR16ri8_NF_ND)
+ENTRY(OR32mi_NF_ND, OR32mi8_NF_ND)
+ENTRY(OR32ri_NF_ND, OR32ri8_NF_ND)
+ENTRY(OR64mi32_NF_ND, OR64mi8_NF_ND)
+ENTRY(OR64ri32_NF_ND, OR64ri8_NF_ND)
+ENTRY(SUB16mi_NF_ND, SUB16mi8_NF_ND)
+ENTRY(SUB16ri_NF_ND, SUB16ri8_NF_ND)
+ENTRY(SUB32mi_NF_ND, SUB32mi8_NF_ND)
+ENTRY(SUB32ri_NF_ND, SUB32ri8_NF_ND)
+ENTRY(SUB64mi32_NF_ND, SUB64mi8_NF_ND)
+ENTRY(SUB64ri32_NF_ND, SUB64ri8_NF_ND)
+ENTRY(XOR16mi_NF_ND, XOR16mi8_NF_ND)
+ENTRY(XOR16ri_NF_ND, XOR16ri8_NF_ND)
+ENTRY(XOR32mi_NF_ND, XOR32mi8_NF_ND)
+ENTRY(XOR32ri_NF_ND, XOR32ri8_NF_ND)
+ENTRY(XOR64mi32_NF_ND, XOR64mi8_NF_ND)
+ENTRY(XOR64ri32_NF_ND, XOR64ri8_NF_ND)
 #undef ENTRY
diff --git a/llvm/test/CodeGen/X86/apx/adc.ll b/llvm/test/CodeGen/X86/apx/adc.ll
index 342d64e6bca009c..c1ae67f5273846b 100644
--- a/llvm/test/CodeGen/X86/apx/adc.ll
+++ b/llvm/test/CodeGen/X86/apx/adc.ll
@@ -112,8 +112,8 @@ define i64 @adc64rm(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
 define i16 @adc16ri8(i16 %a, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0xd7,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xd7,0x00]
 ; CHECK-NEXT:    addl $123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -127,8 +127,8 @@ define i16 @adc16ri8(i16 %a, i16 %x, i16 %y) nounwind {
 define i32 @adc32ri8(i32 %a, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: adc32ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
-; CHECK-NEXT:    adcl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xd7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xd7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %s = add i32 %a, 123
   %k = icmp ugt i32 %x, %y
@@ -140,8 +140,8 @@ define i32 @adc32ri8(i32 %a, i32 %x, i32 %y) nounwind {
 define i64 @adc64ri8(i64 %a, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: adc64ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
-; CHECK-NEXT:    adcq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xd7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xd7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %s = add i64 %a, 123
   %k = icmp ugt i64 %x, %y
@@ -166,8 +166,8 @@ define i8 @adc8ri(i8 %a, i8 %x, i8 %y) nounwind {
 define i16 @adc16ri(i16 %a, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16ri:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0xd7,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xd7,0x00]
 ; CHECK-NEXT:    addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x4D2
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
@@ -266,8 +266,8 @@ define i64 @adc64mr(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
 define i16 @adc16mi8(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0x17,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
 ; CHECK-NEXT:    addl $123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -282,8 +282,8 @@ define i16 @adc16mi8(ptr %ptr, i16 %x, i16 %y) nounwind {
 define i32 @adc32mi8(ptr %ptr, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: adc32mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
-; CHECK-NEXT:    adcl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x17,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x17,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %a = load i32, ptr %ptr
   %s = add i32 %a, 123
@@ -296,8 +296,8 @@ define i32 @adc32mi8(ptr %ptr, i32 %x, i32 %y) nounwind {
 define i64 @adc64mi8(ptr %ptr, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: adc64mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
-; CHECK-NEXT:    adcq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x17,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x17,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %a = load i64, ptr %ptr
   %s = add i64 %a, 123
@@ -324,8 +324,8 @@ define i8 @adc8mi(ptr %ptr, i8 %x, i8 %y) nounwind {
 define i16 @adc16mi(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16mi:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0x17,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
 ; CHECK-NEXT:    addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x4D2
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
@@ -446,8 +446,8 @@ define void @adc8mi_legacy(ptr %ptr, i8 %x, i8 %y) nounwind {
 define void @adc16mi_legacy(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16mi_legacy:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0x17,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
 ; CHECK-NEXT:    addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x4D2
 ; CHECK-NEXT:    movw %ax, (%rdi) # encoding: [0x66,0x89,0x07]
diff --git a/llvm/test/CodeGen/X86/apx/add.ll b/llvm/test/CodeGen/X86/apx/add.ll
index a42f872b93e16fa..cdb29a70770e4b4 100644
--- a/llvm/test/CodeGen/X86/apx/add.ll
+++ b/llvm/test/CodeGen/X86/apx/add.ll
@@ -89,7 +89,7 @@ entry:
 define i16 @add16ri8(i16 noundef %a) {
 ; CHECK-LABEL: add16ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
@@ -100,7 +100,7 @@ entry:
 define i32 @add32ri8(i32 noundef %a) {
 ; CHECK-LABEL: add32ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %add = add i32 %a, 123
@@ -110,7 +110,7 @@ entry:
 define i64 @add64ri8(i64 noundef %a) {
 ; CHECK-LABEL: add64ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %add = add i64 %a, 123
@@ -221,7 +221,7 @@ entry:
 define i32 @add32mi8(ptr %a) {
 ; CHECK-LABEL: add32mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x07,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x07,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i32, ptr %a
@@ -232,7 +232,7 @@ entry:
 define i64 @add64mi8(ptr %a) {
 ; CHECK-LABEL: add64mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x07,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x07,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i64, ptr %a
@@ -405,7 +405,7 @@ entry:
 define i16 @addflag16ri8(i16 noundef %a) {
 ; CHECK-LABEL: addflag16ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addw $123, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xc7,0x7b,0x00]
+; CHECK-NEXT:    addw $123, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    movl $65535, %eax # encoding: [0xb8,0xff,0xff,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0xFFFF
 ; CHECK-NEXT:    cmovael %ecx, %eax # encoding: [0x0f,0x43,0xc1]
@@ -419,7 +419,7 @@ entry:
 define i32 @addflag32ri8(i32 noundef %a) {
 ; CHECK-LABEL: addflag32ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    movl $-1, %eax # encoding: [0xb8,0xff,0xff,0xff,0xff]
 ; CHECK-NEXT:    cmovael %ecx, %eax # encoding: [0x0f,0x43,0xc1]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -431,7 +431,7 @@ entry:
 define i64 @addflag64ri8(i64 noundef %a) {
 ; CHECK-LABEL: addflag64ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    movq $-1, %rax # encoding: [0x48,0xc7,0xc0,0xff,0xff,0xff,0xff]
 ; CHECK-NEXT:    cmovaeq %rcx, %rax # encoding: [0x48,0x0f,0x43,0xc1]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
diff --git a/llvm/test/CodeGen/X86/apx/and.ll b/llvm/test/CodeGen/X86/apx/and.ll
index b7c1a851c07d634..af8f4119ac054d3 100644
--- a/llvm/test/CodeGen/X86/apx/and.ll
+++ b/llvm/test/CodeGen/X86/apx/and.ll
@@ -90,7 +90,7 @@ entry:
 define i16 @and16ri8(i16 noundef %a) {
 ; CHECK-LABEL: and16ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
@@ -101,7 +101,7 @@ entry:
 define i32 @and32ri8(i32 noundef %a) {
 ; CHECK-LABEL: and32ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %and = and i32 %a, 123
@@ -111,7 +111,7 @@ entry:
 define i64 @and64ri8(i64 noundef %a) {
 ; CHECK-LABEL: and64ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %and = and i64 %a, 123
@@ -222,7 +222,7 @@ entry:
 define i32 @and32mi8(ptr %a) {
 ; CHECK-LABEL: and32mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x27,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x27,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i32, ptr %a
@@ -482,7 +482,7 @@ define i1 @andflag64ri(i64 %a) {
 define i1 @andflag16ri8(i16 %a) {
 ; CHECK-LABEL: andflag16ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xe7,0x84,0xff]
+; CHECK-NEXT:    andw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xe7,0x84]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
@@ -497,7 +497,7 @@ define i1 @andflag16ri8(i16 %a) {
 define i1 @andflag32ri8(i32 %a) {
 ; CHECK-LABEL: andflag32ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x83,0xe7,0x7b]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
@@ -511,7 +511,7 @@ define i1 @andflag32ri8(i32 %a) {
 define i1 @andflag64ri8(i64 %a) {
 ; CHECK-LABEL: andflag64ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xe7,0x7b]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
diff --git a/llvm/test/CodeGen/X86/apx/or.ll b/llvm/test/CodeGen/X86/apx/or.ll
index 1219e74074a96dd..3d024e962400fad 100644
--- a/llvm/test/CodeGen/X86/apx/or.ll
+++ b/llvm/test/CodeGen/X86/apx/or.ll
@@ -90,7 +90,7 @@ entry:
 define i16 @or16ri8(i16 noundef %a) {
 ; CHECK-LABEL: or16ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xcf,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xcf,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
@@ -101,7 +101,7 @@ entry:
 define i32 @or32ri8(i32 noundef %a) {
 ; CHECK-LABEL: or32ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xcf,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xcf,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %or = or i32 %a, 123
@@ -111,7 +111,7 @@ entry:
 define i64 @or64ri8(i64 noundef %a) {
 ; CHECK-LABEL: or64ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xcf,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xcf,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %or = or i64 %a, 123
@@ -222,7 +222,7 @@ entry:
 define i32 @or32mi8(ptr %a) {
 ; CHECK-LABEL: or32mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x0f,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x0f,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i32, ptr %a
@@ -233,7 +233,7 @@ entry:
 define i64 @or64mi8(ptr %a) {
 ; CHECK-LABEL: or64mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x0f,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x0f,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i64, ptr %a
@@ -480,7 +480,7 @@ define i1 @orflag64ri(i64 %a) {
 define i1 @orflag16ri8(i16 %a) {
 ; CHECK-LABEL: orflag16ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    orw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xcf,0x84,0xff]
+; CHECK-NEXT:    orw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xcf,0x84]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
@@ -495,7 +495,7 @@ define i1 @orflag16ri8(i16 %a) {
 define i1 @orflag32ri8(i32 %a) {
 ; CHECK-LABEL: orflag32ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    orl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x81,0xcf,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x83,0xcf,0x7b]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
@@ -509,7 +509,7 @@ define i1 @orflag32ri8(i32 %a) {
 define i1 @orflag64ri8(i64 %a) {
 ; CHECK-LABEL: orflag64ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    orq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xcf,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xcf,0x7b]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
diff --git a/llvm/test/CodeGen/X86/apx/sbb.ll b/llvm/test/CodeGen/X86/apx/sbb.ll
index 778fea04b62b5f8..e1834d1c2f5d3b3 100644
--- a/llvm/test/CodeGen/X86/apx/sbb.ll
+++ b/llvm/test/CodeGen/X86/apx/sbb.ll
@@ -112,8 +112,8 @@ define i64 @sbb64rm(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
 define i16 @sbb16ri8(i16 %a, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: sbb16ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    sbbw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0xdf,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addl $-123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x85]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -127,8 +127,8 @@ define i16 @sbb16ri8(i16 %a, i16 %x, i16 %y) nounwind {
 define i32 @sbb32ri8(i32 %a, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: sbb32ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
-; CHECK-NEXT:    sbbl $0, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xdf,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbl $0, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addl $-123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %s = sub i32 %a, 123
@@ -141,8 +141,8 @@ define i32 @sbb32ri8(i32 %a, i32 %x, i32 %y) nounwind {
 define i64 @sbb64ri8(i64 %a, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: sbb64ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
-; CHECK-NEXT:    sbbq $0, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xdf,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbq $0, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addq $-123, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xc0,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %s = sub i64 %a, 123
@@ -169,8 +169,8 @@ define i8 @sbb8ri(i8 %a, i8 %x, i8 %y) nounwind {
 define i16 @sbb16ri(i16 %a, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: sbb16ri:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    sbbw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0xdf,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addl $-1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0x2e,0xfb,0xff,0xff]
 ; CHECK-NEXT:    # imm = 0xFB2E
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
@@ -185,8 +185,8 @@ define i16 @sbb16ri(i16 %a, i16 %x, i16 %y) nounwind {
 define i32 @sbb32ri(i32 %a, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: sbb32ri:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
-; CHECK-NEXT:    sbbl $0, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xdf,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbl $0, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addl $-123456, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xc0,0x1d,0xfe,0xff]
 ; CHECK-NEXT:    # imm = 0xFFFE1DC0
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -200,8 +200,8 @@ define i32 @sbb32ri(i32 %a, i32 %x, i32 %y) nounwind {
 define i64 @sbb64ri(i64 %a, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: sbb64ri:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
-; CHECK-NEXT:    sbbq $0, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xdf,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbq $0, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addq $-123456, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x05,0xc0,0x1d,0xfe,0xff]
 ; CHECK-NEXT:    # imm = 0xFFFE1DC0
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -271,8 +271,8 @@ define i64 @sbb64mr(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
 define i16 @sbb16mi8(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: sbb16mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    sbbw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0x1f,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addl $-123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x85]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -287,8 +287,8 @@ define i16 @sbb16mi8(ptr %ptr, i16 %x, i16 %y) nounwind {
 define i32 @sbb32mi8(ptr %ptr, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: sbb32mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
-; CHECK-NEXT:    sbbl $0, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x1f,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbl $0, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addl $-123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %a = load i32, ptr %ptr
@@ -302,8 +302,8 @@ define i32 @sbb32mi8(ptr %ptr, i32 %x, i32 %y) nounwind {
 define i64 @sbb64mi8(ptr %ptr, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: sbb64mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
-; CHECK-NEXT:    sbbq $0, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x1f,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbq $0, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addq $-123, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xc0,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %a = load i64, ptr %ptr
@@ -332,8 +332,8 @@ define i8 @sbb8mi(ptr %ptr, i8 %x, i8 %y) nounwind {
 define i16 @sbb16mi(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: sbb16mi:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    sbbw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0x1f,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addl $-1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0x2e,0xfb,0xff,0xff]
 ; CHECK-NEXT:    # imm = 0xFB2E
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
@@ -349,8 +349,8 @@ define i16 @sbb16mi(ptr %ptr, i16 %x, i16 %y) nounwind {
 define i32 @sbb32mi(ptr %ptr, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: sbb32mi:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
-; CHECK-NEXT:    sbbl $0, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x1f,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbl $0, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addl $-123456, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xc0,0x1d,0xfe,0xff]
 ; CHECK-NEXT:    # imm = 0xFFFE1DC0
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -365,8 +365,8 @@ define i32 @sbb32mi(ptr %ptr, i32 %x, i32 %y) nounwind {
 define i64 @sbb64mi(ptr %ptr, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: sbb64mi:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
-; CHECK-NEXT:    sbbq $0, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x1f,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    sbbq $0, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addq $-123456, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x05,0xc0,0x1d,0xfe,0xff]
 ; CHECK-NEXT:    # imm = 0xFFFE1DC0
 ; CHECK-NEXT:    retq # encoding: [0xc3]
diff --git a/llvm/test/CodeGen/X86/apx/sub.ll b/llvm/test/CodeGen/X86/apx/sub.ll
index c8e48dbb981af19..4bcfa2586fbf368 100644
--- a/llvm/test/CodeGen/X86/apx/sub.ll
+++ b/llvm/test/CodeGen/X86/apx/sub.ll
@@ -89,7 +89,7 @@ entry:
 define i16 @sub16ri8(i16 noundef %a) {
 ; CHECK-LABEL: sub16ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addl $-123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xc7,0x85,0xff,0xff,0xff]
+; CHECK-NEXT:    addl $-123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xc7,0x85]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
@@ -100,7 +100,7 @@ entry:
 define i32 @sub32ri8(i32 noundef %a) {
 ; CHECK-LABEL: sub32ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addl $-123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xc7,0x85,0xff,0xff,0xff]
+; CHECK-NEXT:    addl $-123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xc7,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %sub = sub i32 %a, 123
@@ -110,7 +110,7 @@ entry:
 define i64 @sub64ri8(i64 noundef %a) {
 ; CHECK-LABEL: sub64ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addq $-123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xc7,0x85,0xff,0xff,0xff]
+; CHECK-NEXT:    addq $-123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xc7,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %sub = sub i64 %a, 123
@@ -223,7 +223,7 @@ entry:
 define i32 @sub32mi8(ptr %a) {
 ; CHECK-LABEL: sub32mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addl $-123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x07,0x85,0xff,0xff,0xff]
+; CHECK-NEXT:    addl $-123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x07,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i32, ptr %a
@@ -234,7 +234,7 @@ entry:
 define i64 @sub64mi8(ptr %a) {
 ; CHECK-LABEL: sub64mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addq $-123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x07,0x85,0xff,0xff,0xff]
+; CHECK-NEXT:    addq $-123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x07,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i64, ptr %a
@@ -406,7 +406,7 @@ define i16 @subflag16ri8(i16 noundef %a) {
 ; CHECK-LABEL: subflag16ri8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorl %ecx, %ecx # encoding: [0x31,0xc9]
-; CHECK-NEXT:    subw $123, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0xef,0x7b,0x00]
+; CHECK-NEXT:    subw $123, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xef,0x7b]
 ; CHECK-NEXT:    cmovbl %ecx, %eax # encoding: [0x0f,0x42,0xc1]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -419,7 +419,7 @@ define i32 @subflag32ri8(i32 noundef %a) {
 ; CHECK-LABEL: subflag32ri8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorl %ecx, %ecx # encoding: [0x31,0xc9]
-; CHECK-NEXT:    subl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xef,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    subl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xef,0x7b]
 ; CHECK-NEXT:    cmovbl %ecx, %eax # encoding: [0x0f,0x42,0xc1]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
@@ -431,7 +431,7 @@ define i64 @subflag64ri8(i64 noundef %a) {
 ; CHECK-LABEL: subflag64ri8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT:    subq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xef,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    subq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xef,0x7b]
 ; CHECK-NEXT:    cmovaeq %rcx, %rax # encoding: [0x48,0x0f,0x43,0xc1]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
diff --git a/llvm/test/CodeGen/X86/apx/xor.ll b/llvm/test/CodeGen/X86/apx/xor.ll
index d75f9f34d7b68d2..d203fbb02782ab4 100644
--- a/llvm/test/CodeGen/X86/apx/xor.ll
+++ b/llvm/test/CodeGen/X86/apx/xor.ll
@@ -90,7 +90,7 @@ entry:
 define i16 @xor16ri8(i16 noundef %a) {
 ; CHECK-LABEL: xor16ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xorl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xf7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    xorl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xf7,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
@@ -101,7 +101,7 @@ entry:
 define i32 @xor32ri8(i32 noundef %a) {
 ; CHECK-LABEL: xor32ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xorl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xf7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    xorl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xf7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %xor = xor i32 %a, 123
@@ -111,7 +111,7 @@ entry:
 define i64 @xor64ri8(i64 noundef %a) {
 ; CHECK-LABEL: xor64ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xorq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xf7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    xorq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xf7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %xor = xor i64 %a, 123
@@ -222,7 +222,7 @@ entry:
 define i32 @xor32mi8(ptr %a) {
 ; CHECK-LABEL: xor32mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xorl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x37,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    xorl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x37,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i32, ptr %a
@@ -233,7 +233,7 @@ entry:
 define i64 @xor64mi8(ptr %a) {
 ; CHECK-LABEL: xor64mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xorq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x37,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    xorq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x37,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i64, ptr %a
@@ -312,7 +312,7 @@ define i1 @xorflag16rr(i16 %a, i16 %b) {
 ; CHECK-LABEL: xorflag16rr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorl %edi, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x31,0xfe]
-; CHECK-NEXT:    xorw $-1, %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xf0,0xff,0xff]
+; CHECK-NEXT:    xorw $-1, %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf0,0xff]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
@@ -373,7 +373,7 @@ define i1 @xorflag16rm(ptr %ptr, i16 %b) {
 ; CHECK-LABEL: xorflag16rm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorw (%rdi), %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x33,0x37]
-; CHECK-NEXT:    xorw $-1, %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xf0,0xff,0xff]
+; CHECK-NEXT:    xorw $-1, %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf0,0xff]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
@@ -480,7 +480,7 @@ define i1 @xorflag64ri(i64 %a) {
 define i1 @xorflag16ri8(i16 %a) {
 ; CHECK-LABEL: xorflag16ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xf7,0x84,0xff]
+; CHECK-NEXT:    xorw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf7,0x84]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
@@ -495,7 +495,7 @@ define i1 @xorflag16ri8(i16 %a) {
 define i1 @xorflag32ri8(i32 %a) {
 ; CHECK-LABEL: xorflag32ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x81,0xf7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    xorl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x83,0xf7,0x7b]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
@@ -509,7 +509,7 @@ define i1 @xorflag32ri8(i32 %a) {
 define i1 @xorflag64ri8(i64 %a) {
 ; CHECK-LABEL: xorflag64ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xf7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    xorq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xf7,0x7b]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte

>From 47c45522174bea16afdd8ffcd02660e591214aa8 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Fri, 26 Jan 2024 01:05:58 -0800
Subject: [PATCH 2/2] support shift compress

---
 .../MCTargetDesc/X86EncodingOptimization.cpp  |  39 +++-
 .../X86EncodingOptimizationForImmediate.def   | 185 ++++++------------
 llvm/test/CodeGen/X86/apx/adc.ll              |  18 +-
 llvm/test/CodeGen/X86/apx/rol.ll              |  16 +-
 llvm/test/CodeGen/X86/apx/sar.ll              |  12 +-
 llvm/test/CodeGen/X86/apx/sbb.ll              |  24 +--
 llvm/test/CodeGen/X86/apx/shift-eflags.ll     |   6 +-
 llvm/test/CodeGen/X86/apx/shr.ll              |  12 +-
 llvm/test/MC/X86/apx/adc-reloc.s              |  22 +++
 llvm/test/MC/X86/apx/add-reloc.s              |  38 ++++
 llvm/test/MC/X86/apx/and-reloc.s              |  38 ++++
 llvm/test/MC/X86/apx/imul-reloc.s             |  18 ++
 llvm/test/MC/X86/apx/or-reloc.s               |  38 ++++
 llvm/test/MC/X86/apx/rcl-encopt.s             |  51 +++++
 llvm/test/MC/X86/apx/rcr-encopt.s             |  50 +++++
 llvm/test/MC/X86/apx/rol-encopt.s             |  98 ++++++++++
 llvm/test/MC/X86/apx/ror-encopt.s             |  98 ++++++++++
 llvm/test/MC/X86/apx/sar-encopt.s             |  98 ++++++++++
 llvm/test/MC/X86/apx/sbb-reloc.s              |  22 +++
 llvm/test/MC/X86/apx/shl-encopt.s             |  98 ++++++++++
 llvm/test/MC/X86/apx/shr-encopt.s             |  98 ++++++++++
 llvm/test/MC/X86/apx/sub-reloc.s              |  38 ++++
 llvm/test/MC/X86/apx/xor-reloc.s              |  38 ++++
 23 files changed, 983 insertions(+), 172 deletions(-)
 create mode 100644 llvm/test/MC/X86/apx/adc-reloc.s
 create mode 100644 llvm/test/MC/X86/apx/add-reloc.s
 create mode 100644 llvm/test/MC/X86/apx/and-reloc.s
 create mode 100644 llvm/test/MC/X86/apx/imul-reloc.s
 create mode 100644 llvm/test/MC/X86/apx/or-reloc.s
 create mode 100644 llvm/test/MC/X86/apx/rcl-encopt.s
 create mode 100644 llvm/test/MC/X86/apx/rcr-encopt.s
 create mode 100644 llvm/test/MC/X86/apx/rol-encopt.s
 create mode 100644 llvm/test/MC/X86/apx/ror-encopt.s
 create mode 100644 llvm/test/MC/X86/apx/sar-encopt.s
 create mode 100644 llvm/test/MC/X86/apx/sbb-reloc.s
 create mode 100644 llvm/test/MC/X86/apx/shl-encopt.s
 create mode 100644 llvm/test/MC/X86/apx/shr-encopt.s
 create mode 100644 llvm/test/MC/X86/apx/sub-reloc.s
 create mode 100644 llvm/test/MC/X86/apx/xor-reloc.s

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
index 03eeef96b502e0d..134206466c542fe 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
@@ -106,6 +106,12 @@ bool X86::optimizeShiftRotateWithImmediateOne(MCInst &MI) {
 #define TO_IMM1(FROM)                                                          \
   case X86::FROM##i:                                                           \
     NewOpc = X86::FROM##1;                                                     \
+    break;                                                                     \
+  case X86::FROM##i_EVEX:                                                      \
+    NewOpc = X86::FROM##1_EVEX;                                                \
+    break;                                                                     \
+  case X86::FROM##i_ND:                                                        \
+    NewOpc = X86::FROM##1_ND;                                                  \
     break;
   switch (MI.getOpcode()) {
   default:
@@ -118,6 +124,31 @@ bool X86::optimizeShiftRotateWithImmediateOne(MCInst &MI) {
     TO_IMM1(RCL16r)
     TO_IMM1(RCL32r)
     TO_IMM1(RCL64r)
+    TO_IMM1(RCR8m)
+    TO_IMM1(RCR16m)
+    TO_IMM1(RCR32m)
+    TO_IMM1(RCR64m)
+    TO_IMM1(RCL8m)
+    TO_IMM1(RCL16m)
+    TO_IMM1(RCL32m)
+    TO_IMM1(RCL64m)
+#undef TO_IMM1
+#define TO_IMM1(FROM)                                                          \
+  case X86::FROM##i:                                                           \
+    NewOpc = X86::FROM##1;                                                     \
+    break;                                                                     \
+  case X86::FROM##i_EVEX:                                                      \
+    NewOpc = X86::FROM##1_EVEX;                                                \
+    break;                                                                     \
+  case X86::FROM##i_NF:                                                        \
+    NewOpc = X86::FROM##1_NF;                                                  \
+    break;                                                                     \
+  case X86::FROM##i_ND:                                                        \
+    NewOpc = X86::FROM##1_ND;                                                  \
+    break;                                                                     \
+  case X86::FROM##i_NF_ND:                                                     \
+    NewOpc = X86::FROM##1_NF_ND;                                               \
+    break;
     TO_IMM1(ROR8r)
     TO_IMM1(ROR16r)
     TO_IMM1(ROR32r)
@@ -138,14 +169,6 @@ bool X86::optimizeShiftRotateWithImmediateOne(MCInst &MI) {
     TO_IMM1(SHL16r)
     TO_IMM1(SHL32r)
     TO_IMM1(SHL64r)
-    TO_IMM1(RCR8m)
-    TO_IMM1(RCR16m)
-    TO_IMM1(RCR32m)
-    TO_IMM1(RCR64m)
-    TO_IMM1(RCL8m)
-    TO_IMM1(RCL16m)
-    TO_IMM1(RCL32m)
-    TO_IMM1(RCL64m)
     TO_IMM1(ROR8m)
     TO_IMM1(ROR16m)
     TO_IMM1(ROR32m)
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def
index e86860e06922e6d..27b6a654e6eb7fa 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def
@@ -12,133 +12,78 @@
 #ifndef ENTRY
 #define ENTRY(LONG, SHORT)
 #endif
-ENTRY(ADC16mi, ADC16mi8)
-ENTRY(ADC16ri, ADC16ri8)
-ENTRY(ADC32mi, ADC32mi8)
-ENTRY(ADC32ri, ADC32ri8)
-ENTRY(ADC64mi32, ADC64mi8)
-ENTRY(ADC64ri32, ADC64ri8)
-ENTRY(SBB16mi, SBB16mi8)
-ENTRY(SBB16ri, SBB16ri8)
-ENTRY(SBB32mi, SBB32mi8)
-ENTRY(SBB32ri, SBB32ri8)
-ENTRY(SBB64mi32, SBB64mi8)
-ENTRY(SBB64ri32, SBB64ri8)
-ENTRY(ADD16mi, ADD16mi8)
-ENTRY(ADD16ri, ADD16ri8)
-ENTRY(ADD32mi, ADD32mi8)
-ENTRY(ADD32ri, ADD32ri8)
-ENTRY(ADD64mi32, ADD64mi8)
-ENTRY(ADD64ri32, ADD64ri8)
-ENTRY(AND16mi, AND16mi8)
-ENTRY(AND16ri, AND16ri8)
-ENTRY(AND32mi, AND32mi8)
-ENTRY(AND32ri, AND32ri8)
-ENTRY(AND64mi32, AND64mi8)
-ENTRY(AND64ri32, AND64ri8)
-ENTRY(OR16mi, OR16mi8)
-ENTRY(OR16ri, OR16ri8)
-ENTRY(OR32mi, OR32mi8)
-ENTRY(OR32ri, OR32ri8)
-ENTRY(OR64mi32, OR64mi8)
-ENTRY(OR64ri32, OR64ri8)
-ENTRY(SUB16mi, SUB16mi8)
-ENTRY(SUB16ri, SUB16ri8)
-ENTRY(SUB32mi, SUB32mi8)
-ENTRY(SUB32ri, SUB32ri8)
-ENTRY(SUB64mi32, SUB64mi8)
-ENTRY(SUB64ri32, SUB64ri8)
-ENTRY(XOR16mi, XOR16mi8)
-ENTRY(XOR16ri, XOR16ri8)
-ENTRY(XOR32mi, XOR32mi8)
-ENTRY(XOR32ri, XOR32ri8)
-ENTRY(XOR64mi32, XOR64mi8)
-ENTRY(XOR64ri32, XOR64ri8)
 ENTRY(CMP16mi, CMP16mi8)
 ENTRY(CMP16ri, CMP16ri8)
 ENTRY(CMP32mi, CMP32mi8)
 ENTRY(CMP32ri, CMP32ri8)
 ENTRY(CMP64mi32, CMP64mi8)
 ENTRY(CMP64ri32, CMP64ri8)
-ENTRY(IMUL16rmi, IMUL16rmi8)
-ENTRY(IMUL16rri, IMUL16rri8)
-ENTRY(IMUL32rmi, IMUL32rmi8)
-ENTRY(IMUL32rri, IMUL32rri8)
-ENTRY(IMUL64rmi32, IMUL64rmi8)
-ENTRY(IMUL64rri32, IMUL64rri8)
 ENTRY(PUSH16i, PUSH16i8)
 ENTRY(PUSH32i, PUSH32i8)
 ENTRY(PUSH64i32, PUSH64i8)
-ENTRY(ADC16mi_ND, ADC16mi8_ND)
-ENTRY(ADC16ri_ND, ADC16ri8_ND)
-ENTRY(ADC32mi_ND, ADC32mi8_ND)
-ENTRY(ADC32ri_ND, ADC32ri8_ND)
-ENTRY(ADC64mi32_ND, ADC64mi8_ND)
-ENTRY(ADC64ri32_ND, ADC64ri8_ND)
-ENTRY(SBB16mi_ND, SBB16mi8_ND)
-ENTRY(SBB16ri_ND, SBB16ri8_ND)
-ENTRY(SBB32mi_ND, SBB32mi8_ND)
-ENTRY(SBB32ri_ND, SBB32ri8_ND)
-ENTRY(SBB64mi32_ND, SBB64mi8_ND)
-ENTRY(SBB64ri32_ND, SBB64ri8_ND)
-ENTRY(ADD16mi_ND, ADD16mi8_ND)
-ENTRY(ADD16ri_ND, ADD16ri8_ND)
-ENTRY(ADD32mi_ND, ADD32mi8_ND)
-ENTRY(ADD32ri_ND, ADD32ri8_ND)
-ENTRY(ADD64mi32_ND, ADD64mi8_ND)
-ENTRY(ADD64ri32_ND, ADD64ri8_ND)
-ENTRY(AND16mi_ND, AND16mi8_ND)
-ENTRY(AND16ri_ND, AND16ri8_ND)
-ENTRY(AND32mi_ND, AND32mi8_ND)
-ENTRY(AND32ri_ND, AND32ri8_ND)
-ENTRY(AND64mi32_ND, AND64mi8_ND)
-ENTRY(AND64ri32_ND, AND64ri8_ND)
-ENTRY(OR16mi_ND, OR16mi8_ND)
-ENTRY(OR16ri_ND, OR16ri8_ND)
-ENTRY(OR32mi_ND, OR32mi8_ND)
-ENTRY(OR32ri_ND, OR32ri8_ND)
-ENTRY(OR64mi32_ND, OR64mi8_ND)
-ENTRY(OR64ri32_ND, OR64ri8_ND)
-ENTRY(SUB16mi_ND, SUB16mi8_ND)
-ENTRY(SUB16ri_ND, SUB16ri8_ND)
-ENTRY(SUB32mi_ND, SUB32mi8_ND)
-ENTRY(SUB32ri_ND, SUB32ri8_ND)
-ENTRY(SUB64mi32_ND, SUB64mi8_ND)
-ENTRY(SUB64ri32_ND, SUB64ri8_ND)
-ENTRY(XOR16mi_ND, XOR16mi8_ND)
-ENTRY(XOR16ri_ND, XOR16ri8_ND)
-ENTRY(XOR32mi_ND, XOR32mi8_ND)
-ENTRY(XOR32ri_ND, XOR32ri8_ND)
-ENTRY(XOR64mi32_ND, XOR64mi8_ND)
-ENTRY(XOR64ri32_ND, XOR64ri8_ND)
-ENTRY(ADD16mi_NF_ND, ADD16mi8_NF_ND)
-ENTRY(ADD16ri_NF_ND, ADD16ri8_NF_ND)
-ENTRY(ADD32mi_NF_ND, ADD32mi8_NF_ND)
-ENTRY(ADD32ri_NF_ND, ADD32ri8_NF_ND)
-ENTRY(ADD64mi32_NF_ND, ADD64mi8_NF_ND)
-ENTRY(ADD64ri32_NF_ND, ADD64ri8_NF_ND)
-ENTRY(AND16mi_NF_ND, AND16mi8_NF_ND)
-ENTRY(AND16ri_NF_ND, AND16ri8_NF_ND)
-ENTRY(AND32mi_NF_ND, AND32mi8_NF_ND)
-ENTRY(AND32ri_NF_ND, AND32ri8_NF_ND)
-ENTRY(AND64mi32_NF_ND, AND64mi8_NF_ND)
-ENTRY(AND64ri32_NF_ND, AND64ri8_NF_ND)
-ENTRY(OR16mi_NF_ND, OR16mi8_NF_ND)
-ENTRY(OR16ri_NF_ND, OR16ri8_NF_ND)
-ENTRY(OR32mi_NF_ND, OR32mi8_NF_ND)
-ENTRY(OR32ri_NF_ND, OR32ri8_NF_ND)
-ENTRY(OR64mi32_NF_ND, OR64mi8_NF_ND)
-ENTRY(OR64ri32_NF_ND, OR64ri8_NF_ND)
-ENTRY(SUB16mi_NF_ND, SUB16mi8_NF_ND)
-ENTRY(SUB16ri_NF_ND, SUB16ri8_NF_ND)
-ENTRY(SUB32mi_NF_ND, SUB32mi8_NF_ND)
-ENTRY(SUB32ri_NF_ND, SUB32ri8_NF_ND)
-ENTRY(SUB64mi32_NF_ND, SUB64mi8_NF_ND)
-ENTRY(SUB64ri32_NF_ND, SUB64ri8_NF_ND)
-ENTRY(XOR16mi_NF_ND, XOR16mi8_NF_ND)
-ENTRY(XOR16ri_NF_ND, XOR16ri8_NF_ND)
-ENTRY(XOR32mi_NF_ND, XOR32mi8_NF_ND)
-ENTRY(XOR32ri_NF_ND, XOR32ri8_NF_ND)
-ENTRY(XOR64mi32_NF_ND, XOR64mi8_NF_ND)
-ENTRY(XOR64ri32_NF_ND, XOR64ri8_NF_ND)
+#define ENTRYS(LONG, SHORT)                                                    \
+  ENTRY(LONG, SHORT)                                                           \
+  ENTRY(LONG##_EVEX, SHORT##_EVEX)                                             \
+  ENTRY(LONG##_NF, SHORT##_NF)                                                 \
+  ENTRY(LONG##_ND, SHORT##_ND)                                                 \
+  ENTRY(LONG##_NF_ND, SHORT##_NF_ND)
+ENTRYS(ADD16mi, ADD16mi8)
+ENTRYS(ADD16ri, ADD16ri8)
+ENTRYS(ADD32mi, ADD32mi8)
+ENTRYS(ADD32ri, ADD32ri8)
+ENTRYS(ADD64mi32, ADD64mi8)
+ENTRYS(ADD64ri32, ADD64ri8)
+ENTRYS(AND16mi, AND16mi8)
+ENTRYS(AND16ri, AND16ri8)
+ENTRYS(AND32mi, AND32mi8)
+ENTRYS(AND32ri, AND32ri8)
+ENTRYS(AND64mi32, AND64mi8)
+ENTRYS(AND64ri32, AND64ri8)
+ENTRYS(OR16mi, OR16mi8)
+ENTRYS(OR16ri, OR16ri8)
+ENTRYS(OR32mi, OR32mi8)
+ENTRYS(OR32ri, OR32ri8)
+ENTRYS(OR64mi32, OR64mi8)
+ENTRYS(OR64ri32, OR64ri8)
+ENTRYS(SUB16mi, SUB16mi8)
+ENTRYS(SUB16ri, SUB16ri8)
+ENTRYS(SUB32mi, SUB32mi8)
+ENTRYS(SUB32ri, SUB32ri8)
+ENTRYS(SUB64mi32, SUB64mi8)
+ENTRYS(SUB64ri32, SUB64ri8)
+ENTRYS(XOR16mi, XOR16mi8)
+ENTRYS(XOR16ri, XOR16ri8)
+ENTRYS(XOR32mi, XOR32mi8)
+ENTRYS(XOR32ri, XOR32ri8)
+ENTRYS(XOR64mi32, XOR64mi8)
+ENTRYS(XOR64ri32, XOR64ri8)
+#undef ENTRYS
+#define ENTRYS(LONG, SHORT)                                                    \
+  ENTRY(LONG, SHORT)                                                           \
+  ENTRY(LONG##_EVEX, SHORT##_EVEX)                                             \
+  ENTRY(LONG##_NF, SHORT##_NF)
+ENTRYS(IMUL16rmi, IMUL16rmi8)
+ENTRYS(IMUL16rri, IMUL16rri8)
+ENTRYS(IMUL32rmi, IMUL32rmi8)
+ENTRYS(IMUL32rri, IMUL32rri8)
+ENTRYS(IMUL64rmi32, IMUL64rmi8)
+ENTRYS(IMUL64rri32, IMUL64rri8)
+#undef ENTRYS
+#define ENTRYS(LONG, SHORT)                                                    \
+  ENTRY(LONG, SHORT)                                                           \
+  ENTRY(LONG##_EVEX, SHORT##_EVEX)                                             \
+  ENTRY(LONG##_ND, SHORT##_ND)
+ENTRYS(ADC16mi, ADC16mi8)
+ENTRYS(ADC16ri, ADC16ri8)
+ENTRYS(ADC32mi, ADC32mi8)
+ENTRYS(ADC32ri, ADC32ri8)
+ENTRYS(ADC64mi32, ADC64mi8)
+ENTRYS(ADC64ri32, ADC64ri8)
+ENTRYS(SBB16mi, SBB16mi8)
+ENTRYS(SBB16ri, SBB16ri8)
+ENTRYS(SBB32mi, SBB32mi8)
+ENTRYS(SBB32ri, SBB32ri8)
+ENTRYS(SBB64mi32, SBB64mi8)
+ENTRYS(SBB64ri32, SBB64ri8)
+#undef ENTRYS
 #undef ENTRY
diff --git a/llvm/test/CodeGen/X86/apx/adc.ll b/llvm/test/CodeGen/X86/apx/adc.ll
index c1ae67f5273846b..621784f86bdedbd 100644
--- a/llvm/test/CodeGen/X86/apx/adc.ll
+++ b/llvm/test/CodeGen/X86/apx/adc.ll
@@ -112,7 +112,7 @@ define i64 @adc64rm(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
 define i16 @adc16ri8(i16 %a, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
 ; CHECK-NEXT:    adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xd7,0x00]
 ; CHECK-NEXT:    addl $123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
@@ -127,7 +127,7 @@ define i16 @adc16ri8(i16 %a, i16 %x, i16 %y) nounwind {
 define i32 @adc32ri8(i32 %a, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: adc32ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
 ; CHECK-NEXT:    adcl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xd7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %s = add i32 %a, 123
@@ -140,7 +140,7 @@ define i32 @adc32ri8(i32 %a, i32 %x, i32 %y) nounwind {
 define i64 @adc64ri8(i64 %a, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: adc64ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
 ; CHECK-NEXT:    adcq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xd7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %s = add i64 %a, 123
@@ -166,7 +166,7 @@ define i8 @adc8ri(i8 %a, i8 %x, i8 %y) nounwind {
 define i16 @adc16ri(i16 %a, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16ri:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
 ; CHECK-NEXT:    adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xd7,0x00]
 ; CHECK-NEXT:    addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x4D2
@@ -266,7 +266,7 @@ define i64 @adc64mr(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
 define i16 @adc16mi8(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
 ; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
 ; CHECK-NEXT:    addl $123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
@@ -282,7 +282,7 @@ define i16 @adc16mi8(ptr %ptr, i16 %x, i16 %y) nounwind {
 define i32 @adc32mi8(ptr %ptr, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: adc32mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
 ; CHECK-NEXT:    adcl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x17,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %a = load i32, ptr %ptr
@@ -296,7 +296,7 @@ define i32 @adc32mi8(ptr %ptr, i32 %x, i32 %y) nounwind {
 define i64 @adc64mi8(ptr %ptr, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: adc64mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
 ; CHECK-NEXT:    adcq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x17,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %a = load i64, ptr %ptr
@@ -324,7 +324,7 @@ define i8 @adc8mi(ptr %ptr, i8 %x, i8 %y) nounwind {
 define i16 @adc16mi(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16mi:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
 ; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
 ; CHECK-NEXT:    addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x4D2
@@ -446,7 +446,7 @@ define void @adc8mi_legacy(ptr %ptr, i8 %x, i8 %y) nounwind {
 define void @adc16mi_legacy(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16mi_legacy:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
 ; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
 ; CHECK-NEXT:    addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x4D2
diff --git a/llvm/test/CodeGen/X86/apx/rol.ll b/llvm/test/CodeGen/X86/apx/rol.ll
index ebc08ef7f325bb7..58ddc55ab6aba1d 100644
--- a/llvm/test/CodeGen/X86/apx/rol.ll
+++ b/llvm/test/CodeGen/X86/apx/rol.ll
@@ -4,7 +4,7 @@
 define i8 @rol8m1(ptr %ptr) {
 ; CHECK-LABEL: rol8m1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    rolb $1, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xc0,0x07,0x01]
+; CHECK-NEXT:    rolb (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x07]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %a = load i8, ptr %ptr
@@ -27,7 +27,7 @@ define i8 @rol8m1_intrinsic(ptr %ptr)  {
 define i16 @rol16m1(ptr %ptr) {
 ; CHECK-LABEL: rol16m1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    rolw $1, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xc1,0x07,0x01]
+; CHECK-NEXT:    rolw (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0x07]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %a = load i16, ptr %ptr
@@ -50,7 +50,7 @@ define i16 @rol16m1_intrinsic(ptr %ptr)  {
 define i32 @rol32m1(ptr %ptr) {
 ; CHECK-LABEL: rol32m1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    roll $1, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0x07,0x01]
+; CHECK-NEXT:    roll (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x07]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %a = load i32, ptr %ptr
@@ -73,7 +73,7 @@ define i32 @rol32m1_intrinsic(ptr %ptr)  {
 define i64 @rol64m1(ptr %ptr) {
 ; CHECK-LABEL: rol64m1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    rolq $1, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0x07,0x01]
+; CHECK-NEXT:    rolq (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x07]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %a = load i64, ptr %ptr
@@ -212,7 +212,7 @@ entry:
 define i8 @rol8r1(i8 noundef %a) {
 ; CHECK-LABEL: rol8r1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    rolb $1, %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xc0,0xc7,0x01]
+; CHECK-NEXT:    rolb %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xc7]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %0 = shl i8 %a, 1
@@ -233,7 +233,7 @@ define i8 @rol8r1_intrinsic(i8 noundef %a)  {
 define i16 @rol16r1(i16 noundef %a) {
 ; CHECK-LABEL: rol16r1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    rolw $1, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xc1,0xc7,0x01]
+; CHECK-NEXT:    rolw %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0xc7]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %0 = shl i16 %a, 1
@@ -254,7 +254,7 @@ define i16 @rol16r1_intrinsic(i16 noundef %a)  {
 define i32 @rol32r1(i32 noundef %a) {
 ; CHECK-LABEL: rol32r1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    roll $1, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0xc7,0x01]
+; CHECK-NEXT:    roll %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xc7]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %0 = shl i32 %a, 1
@@ -275,7 +275,7 @@ define i32 @rol32r1_intrinsic(i32 noundef %a)  {
 define i64 @rol64r1(i64 noundef %a) {
 ; CHECK-LABEL: rol64r1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    rolq $1, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xc7,0x01]
+; CHECK-NEXT:    rolq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xc7]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %0 = shl i64 %a, 1
diff --git a/llvm/test/CodeGen/X86/apx/sar.ll b/llvm/test/CodeGen/X86/apx/sar.ll
index 091a0eec321cf20..6a14aa6a5056382 100644
--- a/llvm/test/CodeGen/X86/apx/sar.ll
+++ b/llvm/test/CodeGen/X86/apx/sar.ll
@@ -4,7 +4,7 @@
 define i8 @sar8m1(ptr %ptr) {
 ; CHECK-LABEL: sar8m1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sarb $1, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xc0,0x3f,0x01]
+; CHECK-NEXT:    sarb (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x3f]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %a = load i8, ptr %ptr
@@ -28,7 +28,7 @@ entry:
 define i32 @sar32m1(ptr %ptr) {
 ; CHECK-LABEL: sar32m1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sarl $1, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0x3f,0x01]
+; CHECK-NEXT:    sarl (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x3f]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %a = load i32, ptr %ptr
@@ -39,7 +39,7 @@ entry:
 define i64 @sar64m1(ptr %ptr) {
 ; CHECK-LABEL: sar64m1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sarq $1, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0x3f,0x01]
+; CHECK-NEXT:    sarq (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x3f]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %a = load i64, ptr %ptr
@@ -208,7 +208,7 @@ entry:
 define i8 @sar8r1(i8 noundef %a) {
 ; CHECK-LABEL: sar8r1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sarb $1, %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xc0,0xff,0x01]
+; CHECK-NEXT:    sarb %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xff]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %sar = ashr i8 %a, 1
@@ -230,7 +230,7 @@ entry:
 define i32 @sar32r1(i32 noundef %a) {
 ; CHECK-LABEL: sar32r1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sarl $1, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0xff,0x01]
+; CHECK-NEXT:    sarl %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xff]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %sar = ashr i32 %a, 1
@@ -240,7 +240,7 @@ entry:
 define i64 @sar64r1(i64 noundef %a) {
 ; CHECK-LABEL: sar64r1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sarq $1, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xff,0x01]
+; CHECK-NEXT:    sarq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xff]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %sar = ashr i64 %a, 1
diff --git a/llvm/test/CodeGen/X86/apx/sbb.ll b/llvm/test/CodeGen/X86/apx/sbb.ll
index e1834d1c2f5d3b3..b9032f92f8b20e7 100644
--- a/llvm/test/CodeGen/X86/apx/sbb.ll
+++ b/llvm/test/CodeGen/X86/apx/sbb.ll
@@ -112,7 +112,7 @@ define i64 @sbb64rm(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
 define i16 @sbb16ri8(i16 %a, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: sbb16ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
 ; CHECK-NEXT:    sbbw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addl $-123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x85]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
@@ -127,7 +127,7 @@ define i16 @sbb16ri8(i16 %a, i16 %x, i16 %y) nounwind {
 define i32 @sbb32ri8(i32 %a, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: sbb32ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
 ; CHECK-NEXT:    sbbl $0, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addl $-123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -141,7 +141,7 @@ define i32 @sbb32ri8(i32 %a, i32 %x, i32 %y) nounwind {
 define i64 @sbb64ri8(i64 %a, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: sbb64ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
 ; CHECK-NEXT:    sbbq $0, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addq $-123, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xc0,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -169,7 +169,7 @@ define i8 @sbb8ri(i8 %a, i8 %x, i8 %y) nounwind {
 define i16 @sbb16ri(i16 %a, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: sbb16ri:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
 ; CHECK-NEXT:    sbbw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addl $-1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0x2e,0xfb,0xff,0xff]
 ; CHECK-NEXT:    # imm = 0xFB2E
@@ -185,7 +185,7 @@ define i16 @sbb16ri(i16 %a, i16 %x, i16 %y) nounwind {
 define i32 @sbb32ri(i32 %a, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: sbb32ri:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
 ; CHECK-NEXT:    sbbl $0, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addl $-123456, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xc0,0x1d,0xfe,0xff]
 ; CHECK-NEXT:    # imm = 0xFFFE1DC0
@@ -200,7 +200,7 @@ define i32 @sbb32ri(i32 %a, i32 %x, i32 %y) nounwind {
 define i64 @sbb64ri(i64 %a, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: sbb64ri:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
 ; CHECK-NEXT:    sbbq $0, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xdf,0x00]
 ; CHECK-NEXT:    addq $-123456, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x05,0xc0,0x1d,0xfe,0xff]
 ; CHECK-NEXT:    # imm = 0xFFFE1DC0
@@ -271,7 +271,7 @@ define i64 @sbb64mr(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
 define i16 @sbb16mi8(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: sbb16mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
 ; CHECK-NEXT:    sbbw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addl $-123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x85]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
@@ -287,7 +287,7 @@ define i16 @sbb16mi8(ptr %ptr, i16 %x, i16 %y) nounwind {
 define i32 @sbb32mi8(ptr %ptr, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: sbb32mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
 ; CHECK-NEXT:    sbbl $0, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addl $-123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -302,7 +302,7 @@ define i32 @sbb32mi8(ptr %ptr, i32 %x, i32 %y) nounwind {
 define i64 @sbb64mi8(ptr %ptr, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: sbb64mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
 ; CHECK-NEXT:    sbbq $0, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addq $-123, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xc0,0x85]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -332,7 +332,7 @@ define i8 @sbb8mi(ptr %ptr, i8 %x, i8 %y) nounwind {
 define i16 @sbb16mi(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: sbb16mi:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
 ; CHECK-NEXT:    sbbw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addl $-1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0x2e,0xfb,0xff,0xff]
 ; CHECK-NEXT:    # imm = 0xFB2E
@@ -349,7 +349,7 @@ define i16 @sbb16mi(ptr %ptr, i16 %x, i16 %y) nounwind {
 define i32 @sbb32mi(ptr %ptr, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: sbb32mi:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
 ; CHECK-NEXT:    sbbl $0, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addl $-123456, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xc0,0x1d,0xfe,0xff]
 ; CHECK-NEXT:    # imm = 0xFFFE1DC0
@@ -365,7 +365,7 @@ define i32 @sbb32mi(ptr %ptr, i32 %x, i32 %y) nounwind {
 define i64 @sbb64mi(ptr %ptr, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: sbb64mi:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
 ; CHECK-NEXT:    sbbq $0, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x1f,0x00]
 ; CHECK-NEXT:    addq $-123456, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x05,0xc0,0x1d,0xfe,0xff]
 ; CHECK-NEXT:    # imm = 0xFFFE1DC0
diff --git a/llvm/test/CodeGen/X86/apx/shift-eflags.ll b/llvm/test/CodeGen/X86/apx/shift-eflags.ll
index ed181aa11623845..f34dc6c05dad986 100644
--- a/llvm/test/CodeGen/X86/apx/shift-eflags.ll
+++ b/llvm/test/CodeGen/X86/apx/shift-eflags.ll
@@ -89,7 +89,7 @@ define i32 @ashr_const1(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
 ; CHECK-LABEL: ashr_const1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edx, %eax
-; CHECK-NEXT:    sarl $1, %edi, %edx
+; CHECK-NEXT:    sarl %edi, %edx
 ; CHECK-NEXT:    cmovnel %ecx, %eax
 ; CHECK-NEXT:    retq
   %s = ashr i32 %a0, 1
@@ -130,7 +130,7 @@ define i32 @shl_const1(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
 define i32 @ashr_const1_self_select(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
 ; CHECK-LABEL: ashr_const1_self_select:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sarl $1, %edi, %eax
+; CHECK-NEXT:    sarl %edi, %eax
 ; CHECK-NEXT:    cmovnel %edx, %eax
 ; CHECK-NEXT:    retq
   %s = ashr i32 %a0, 1
@@ -143,7 +143,7 @@ define i32 @ashr_const1_self_select(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
 define i32 @lshr_const1_self_select(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
 ; CHECK-LABEL: lshr_const1_self_select:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    shrl $1, %edi, %eax
+; CHECK-NEXT:    shrl %edi, %eax
 ; CHECK-NEXT:    cmovnel %edx, %eax
 ; CHECK-NEXT:    retq
   %s = lshr i32 %a0, 1
diff --git a/llvm/test/CodeGen/X86/apx/shr.ll b/llvm/test/CodeGen/X86/apx/shr.ll
index d633251fc6a2599..a7e02d8586f49d4 100644
--- a/llvm/test/CodeGen/X86/apx/shr.ll
+++ b/llvm/test/CodeGen/X86/apx/shr.ll
@@ -4,7 +4,7 @@
 define i8 @shr8m1(ptr %ptr) {
 ; CHECK-LABEL: shr8m1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    shrb $1, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xc0,0x2f,0x01]
+; CHECK-NEXT:    shrb (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x2f]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %a = load i8, ptr %ptr
@@ -28,7 +28,7 @@ entry:
 define i32 @shr32m1(ptr %ptr) {
 ; CHECK-LABEL: shr32m1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    shrl $1, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0x2f,0x01]
+; CHECK-NEXT:    shrl (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x2f]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %a = load i32, ptr %ptr
@@ -39,7 +39,7 @@ entry:
 define i64 @shr64m1(ptr %ptr) {
 ; CHECK-LABEL: shr64m1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    shrq $1, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0x2f,0x01]
+; CHECK-NEXT:    shrq (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x2f]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %a = load i64, ptr %ptr
@@ -208,7 +208,7 @@ entry:
 define i8 @shr8r1(i8 noundef %a) {
 ; CHECK-LABEL: shr8r1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    shrb $1, %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xc0,0xef,0x01]
+; CHECK-NEXT:    shrb %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xef]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %shr = lshr i8 %a, 1
@@ -230,7 +230,7 @@ entry:
 define i32 @shr32r1(i32 noundef %a) {
 ; CHECK-LABEL: shr32r1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    shrl $1, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0xef,0x01]
+; CHECK-NEXT:    shrl %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xef]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %shr = lshr i32 %a, 1
@@ -240,7 +240,7 @@ entry:
 define i64 @shr64r1(i64 noundef %a) {
 ; CHECK-LABEL: shr64r1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    shrq $1, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x01]
+; CHECK-NEXT:    shrq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xef]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %shr = lshr i64 %a, 1
diff --git a/llvm/test/MC/X86/apx/adc-reloc.s b/llvm/test/MC/X86/apx/adc-reloc.s
new file mode 100644
index 000000000000000..c7695abaac4ede5
--- /dev/null
+++ b/llvm/test/MC/X86/apx/adc-reloc.s
@@ -0,0 +1,22 @@
+// RUN: llvm-mc -triple x86_64-linux-gnu -filetype=obj %s | llvm-readobj -r - | FileCheck %s
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section ({{[0-9]+}}) .rela.text {
+{evex}  adcb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+adcb $foo, %al, %bl                         // CHECK-NEXT:     R_X86_64_8
+{evex}  adcb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8   
+adcb $foo, 123(%r8,%rax,4), %bl             // CHECK-NEXT:     R_X86_64_8
+{evex}  adcw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+adcw $foo, %ax, %bx                         // CHECK-NEXT:     R_X86_64_16
+{evex}  adcw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+adcw $foo, 123(%r8,%rax,4), %bx             // CHECK-NEXT:     R_X86_64_16
+{evex}  adcl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+adcl $foo, %eax, %ebx                       // CHECK-NEXT:     R_X86_64_32
+{evex}  adcl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+adcl $foo, 123(%r8,%rax,4), %ebx            // CHECK-NEXT:     R_X86_64_32
+{evex}  adcq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+adcq $foo, %rax, %rbx                       // CHECK-NEXT:     R_X86_64_32S
+{evex}  adcq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+adcq $foo, 123(%r8,%rax,4), %rbx            // CHECK-NEXT:     R_X86_64_32S
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
diff --git a/llvm/test/MC/X86/apx/add-reloc.s b/llvm/test/MC/X86/apx/add-reloc.s
new file mode 100644
index 000000000000000..138bba6b2fcaeba
--- /dev/null
+++ b/llvm/test/MC/X86/apx/add-reloc.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple x86_64-linux-gnu -filetype=obj %s | llvm-readobj -r - | FileCheck %s
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section ({{[0-9]+}}) .rela.text {
+{evex}  addb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+{nf}    addb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+addb $foo, %al, %bl                         // CHECK-NEXT:     R_X86_64_8
+{nf}    addb $foo, %al, %bl                 // CHECK-NEXT:     R_X86_64_8
+{evex}  addb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8   
+{nf}    addb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8
+addb $foo, 123(%r8,%rax,4), %bl             // CHECK-NEXT:     R_X86_64_8
+{nf}    addb $foo, 123(%r8,%rax,4), %bl     // CHECK-NEXT:     R_X86_64_8
+{evex}  addw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+{nf}    addw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+addw $foo, %ax, %bx                         // CHECK-NEXT:     R_X86_64_16
+{nf}    addw $foo, %ax, %bx                 // CHECK-NEXT:     R_X86_64_16
+{evex}  addw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+{nf}    addw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+addw $foo, 123(%r8,%rax,4), %bx             // CHECK-NEXT:     R_X86_64_16
+{nf}    addw $foo, 123(%r8,%rax,4), %bx     // CHECK-NEXT:     R_X86_64_16
+{evex}  addl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+{nf}    addl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+addl $foo, %eax, %ebx                       // CHECK-NEXT:     R_X86_64_32
+{nf}    addl $foo, %eax, %ebx               // CHECK-NEXT:     R_X86_64_32
+{evex}  addl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+{nf}    addl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+addl $foo, 123(%r8,%rax,4), %ebx            // CHECK-NEXT:     R_X86_64_32
+{nf}    addl $foo, 123(%r8,%rax,4), %ebx    // CHECK-NEXT:     R_X86_64_32
+{evex}  addq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+{nf}    addq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+addq $foo, %rax, %rbx                       // CHECK-NEXT:     R_X86_64_32S
+{nf}    addq $foo, %rax, %rbx               // CHECK-NEXT:     R_X86_64_32S
+{evex}  addq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+{nf}    addq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+addq $foo, 123(%r8,%rax,4), %rbx            // CHECK-NEXT:     R_X86_64_32S
+{nf}    addq $foo, 123(%r8,%rax,4), %rbx    // CHECK-NEXT:     R_X86_64_32S
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
diff --git a/llvm/test/MC/X86/apx/and-reloc.s b/llvm/test/MC/X86/apx/and-reloc.s
new file mode 100644
index 000000000000000..24e7e7893e68ac1
--- /dev/null
+++ b/llvm/test/MC/X86/apx/and-reloc.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple x86_64-linux-gnu -filetype=obj %s | llvm-readobj -r - | FileCheck %s
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section ({{[0-9]+}}) .rela.text {
+{evex}  andb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+{nf}    andb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+andb $foo, %al, %bl                         // CHECK-NEXT:     R_X86_64_8
+{nf}    andb $foo, %al, %bl                 // CHECK-NEXT:     R_X86_64_8
+{evex}  andb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8   
+{nf}    andb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8
+andb $foo, 123(%r8,%rax,4), %bl             // CHECK-NEXT:     R_X86_64_8
+{nf}    andb $foo, 123(%r8,%rax,4), %bl     // CHECK-NEXT:     R_X86_64_8
+{evex}  andw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+{nf}    andw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+andw $foo, %ax, %bx                         // CHECK-NEXT:     R_X86_64_16
+{nf}    andw $foo, %ax, %bx                 // CHECK-NEXT:     R_X86_64_16
+{evex}  andw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+{nf}    andw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+andw $foo, 123(%r8,%rax,4), %bx             // CHECK-NEXT:     R_X86_64_16
+{nf}    andw $foo, 123(%r8,%rax,4), %bx     // CHECK-NEXT:     R_X86_64_16
+{evex}  andl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+{nf}    andl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+andl $foo, %eax, %ebx                       // CHECK-NEXT:     R_X86_64_32
+{nf}    andl $foo, %eax, %ebx               // CHECK-NEXT:     R_X86_64_32
+{evex}  andl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+{nf}    andl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+andl $foo, 123(%r8,%rax,4), %ebx            // CHECK-NEXT:     R_X86_64_32
+{nf}    andl $foo, 123(%r8,%rax,4), %ebx    // CHECK-NEXT:     R_X86_64_32
+{evex}  andq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+{nf}    andq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+andq $foo, %rax, %rbx                       // CHECK-NEXT:     R_X86_64_32S
+{nf}    andq $foo, %rax, %rbx               // CHECK-NEXT:     R_X86_64_32S
+{evex}  andq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+{nf}    andq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+andq $foo, 123(%r8,%rax,4), %rbx            // CHECK-NEXT:     R_X86_64_32S
+{nf}    andq $foo, 123(%r8,%rax,4), %rbx    // CHECK-NEXT:     R_X86_64_32S
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
diff --git a/llvm/test/MC/X86/apx/imul-reloc.s b/llvm/test/MC/X86/apx/imul-reloc.s
new file mode 100644
index 000000000000000..fefcafe367b4b27
--- /dev/null
+++ b/llvm/test/MC/X86/apx/imul-reloc.s
@@ -0,0 +1,18 @@
+// RUN: llvm-mc -triple x86_64-linux-gnu -filetype=obj %s | llvm-readobj -r - | FileCheck %s
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section ({{[0-9]+}}) .rela.text {
+{evex}  subw $foo, %ax, %ax                 // CHECK-NEXT:     R_X86_64_16
+{nf}    subw $foo, %ax, %ax                 // CHECK-NEXT:     R_X86_64_16
+{evex}  subw $foo, 123(%r8,%rax,4), %ax     // CHECK-NEXT:     R_X86_64_16
+{nf}    subw $foo, 123(%r8,%rax,4), %ax     // CHECK-NEXT:     R_X86_64_16
+{evex}  subl $foo, %eax, %eax               // CHECK-NEXT:     R_X86_64_32
+{nf}    subl $foo, %eax, %eax               // CHECK-NEXT:     R_X86_64_32
+{evex}  subl $foo, 123(%r8,%rax,4), %eax    // CHECK-NEXT:     R_X86_64_32
+{nf}    subl $foo, 123(%r8,%rax,4), %eax    // CHECK-NEXT:     R_X86_64_32
+{evex}  subq $foo, %rax, %rax               // CHECK-NEXT:     R_X86_64_32S
+{nf}    subq $foo, %rax, %rax               // CHECK-NEXT:     R_X86_64_32S
+{evex}  subq $foo, 123(%r8,%rax,4), %rax    // CHECK-NEXT:     R_X86_64_32S
+{nf}    subq $foo, 123(%r8,%rax,4), %rax    // CHECK-NEXT:     R_X86_64_32S
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
diff --git a/llvm/test/MC/X86/apx/or-reloc.s b/llvm/test/MC/X86/apx/or-reloc.s
new file mode 100644
index 000000000000000..85af7f7537dc0f8
--- /dev/null
+++ b/llvm/test/MC/X86/apx/or-reloc.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple x86_64-linux-gnu -filetype=obj %s | llvm-readobj -r - | FileCheck %s
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section ({{[0-9]+}}) .rela.text {
+{evex}  orb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+{nf}    orb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+orb $foo, %al, %bl                         // CHECK-NEXT:     R_X86_64_8
+{nf}    orb $foo, %al, %bl                 // CHECK-NEXT:     R_X86_64_8
+{evex}  orb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8   
+{nf}    orb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8
+orb $foo, 123(%r8,%rax,4), %bl             // CHECK-NEXT:     R_X86_64_8
+{nf}    orb $foo, 123(%r8,%rax,4), %bl     // CHECK-NEXT:     R_X86_64_8
+{evex}  orw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+{nf}    orw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+orw $foo, %ax, %bx                         // CHECK-NEXT:     R_X86_64_16
+{nf}    orw $foo, %ax, %bx                 // CHECK-NEXT:     R_X86_64_16
+{evex}  orw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+{nf}    orw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+orw $foo, 123(%r8,%rax,4), %bx             // CHECK-NEXT:     R_X86_64_16
+{nf}    orw $foo, 123(%r8,%rax,4), %bx     // CHECK-NEXT:     R_X86_64_16
+{evex}  orl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+{nf}    orl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+orl $foo, %eax, %ebx                       // CHECK-NEXT:     R_X86_64_32
+{nf}    orl $foo, %eax, %ebx               // CHECK-NEXT:     R_X86_64_32
+{evex}  orl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+{nf}    orl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+orl $foo, 123(%r8,%rax,4), %ebx            // CHECK-NEXT:     R_X86_64_32
+{nf}    orl $foo, 123(%r8,%rax,4), %ebx    // CHECK-NEXT:     R_X86_64_32
+{evex}  orq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+{nf}    orq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+orq $foo, %rax, %rbx                       // CHECK-NEXT:     R_X86_64_32S
+{nf}    orq $foo, %rax, %rbx               // CHECK-NEXT:     R_X86_64_32S
+{evex}  orq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+{nf}    orq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+orq $foo, 123(%r8,%rax,4), %rbx            // CHECK-NEXT:     R_X86_64_32S
+{nf}    orq $foo, 123(%r8,%rax,4), %rbx    // CHECK-NEXT:     R_X86_64_32S
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
diff --git a/llvm/test/MC/X86/apx/rcl-encopt.s b/llvm/test/MC/X86/apx/rcl-encopt.s
new file mode 100644
index 000000000000000..cd7055fa3923af5
--- /dev/null
+++ b/llvm/test/MC/X86/apx/rcl-encopt.s
@@ -0,0 +1,51 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+
+# CHECK: {evex}	rclb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd0,0xd0]
+         {evex}	rclb	$1, %al
+# CHECK: {evex}	rclw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xd1,0xd0]
+         {evex}	rclw	$1, %ax
+# CHECK: {evex}	rcll	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xd0]
+         {evex}	rcll	$1, %eax
+# CHECK: {evex}	rclq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xd1,0xd0]
+         {evex}	rclq	$1, %rax
+# CHECK: rclb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd0,0xd0]
+         rclb	$1, %al, %bl
+# CHECK: rclw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x18,0xd1,0xd0]
+         rclw	$1, %ax, %bx
+# CHECK: rcll	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd1,0xd0]
+         rcll	$1, %eax, %ebx
+# CHECK: rclq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xd0]
+         rclq	$1, %rax, %rbx
+# CHECK: {evex}	rclb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0x54,0x80,0x7b]
+         {evex}	rclb	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	rclw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xd1,0x54,0x80,0x7b]
+         {evex}	rclw	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	rcll	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd1,0x54,0x80,0x7b]
+         {evex}	rcll	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	rclq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0x54,0x80,0x7b]
+         {evex}	rclq	$1, 123(%r8,%rax,4)
+# CHECK: rclb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd0,0x54,0x80,0x7b]
+         rclb	$1, 123(%r8,%rax,4), %bl
+# CHECK: rclw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x18,0xd1,0x54,0x80,0x7b]
+         rclw	$1, 123(%r8,%rax,4), %bx
+# CHECK: rcll	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd1,0x54,0x80,0x7b]
+         rcll	$1, 123(%r8,%rax,4), %ebx
+# CHECK: rclq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x18,0xd1,0x54,0x80,0x7b]
+         rclq	$1, 123(%r8,%rax,4), %rbx
diff --git a/llvm/test/MC/X86/apx/rcr-encopt.s b/llvm/test/MC/X86/apx/rcr-encopt.s
new file mode 100644
index 000000000000000..2061f92e6a6fc89
--- /dev/null
+++ b/llvm/test/MC/X86/apx/rcr-encopt.s
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: {evex}	rcrb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd0,0xd8]
+         {evex}	rcrb	$1, %al
+# CHECK: {evex}	rcrw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xd1,0xd8]
+         {evex}	rcrw	$1, %ax
+# CHECK: {evex}	rcrl	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xd8]
+         {evex}	rcrl	$1, %eax
+# CHECK: {evex}	rcrq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xd1,0xd8]
+         {evex}	rcrq	$1, %rax
+# CHECK: rcrb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd0,0xd8]
+         rcrb	$1, %al, %bl
+# CHECK: rcrw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x18,0xd1,0xd8]
+         rcrw	$1, %ax, %bx
+# CHECK: rcrl	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd1,0xd8]
+         rcrl	$1, %eax, %ebx
+# CHECK: rcrq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xd8]
+         rcrq	$1, %rax, %rbx
+# CHECK: {evex}	rcrb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0x5c,0x80,0x7b]
+         {evex}	rcrb	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	rcrw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xd1,0x5c,0x80,0x7b]
+         {evex}	rcrw	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	rcrl	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd1,0x5c,0x80,0x7b]
+         {evex}	rcrl	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	rcrq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0x5c,0x80,0x7b]
+         {evex}	rcrq	$1, 123(%r8,%rax,4)
+# CHECK: rcrb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd0,0x5c,0x80,0x7b]
+         rcrb	$1, 123(%r8,%rax,4), %bl
+# CHECK: rcrw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x18,0xd1,0x5c,0x80,0x7b]
+         rcrw	$1, 123(%r8,%rax,4), %bx
+# CHECK: rcrl	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd1,0x5c,0x80,0x7b]
+         rcrl	$1, 123(%r8,%rax,4), %ebx
+# CHECK: rcrq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x18,0xd1,0x5c,0x80,0x7b]
+         rcrq	$1, 123(%r8,%rax,4), %rbx
diff --git a/llvm/test/MC/X86/apx/rol-encopt.s b/llvm/test/MC/X86/apx/rol-encopt.s
new file mode 100644
index 000000000000000..d154779d1f62650
--- /dev/null
+++ b/llvm/test/MC/X86/apx/rol-encopt.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: {evex}	rolb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd0,0xc0]
+         {evex}	rolb	$1, %al
+# CHECK: {evex}	rolw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xd1,0xc0]
+         {evex}	rolw	$1, %ax
+# CHECK: {evex}	roll	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xc0]
+         {evex}	roll	$1, %eax
+# CHECK: {evex}	rolq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xd1,0xc0]
+         {evex}	rolq	$1, %rax
+# CHECK: {nf}	rolb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xd0,0xc0]
+         {nf}	rolb	$1, %al
+# CHECK: {nf}	rolw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xd1,0xc0]
+         {nf}	rolw	$1, %ax
+# CHECK: {nf}	roll	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xd1,0xc0]
+         {nf}	roll	$1, %eax
+# CHECK: {nf}	rolq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x0c,0xd1,0xc0]
+         {nf}	rolq	$1, %rax
+# CHECK: rolb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd0,0xc0]
+         rolb	$1, %al, %bl
+# CHECK: rolw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x18,0xd1,0xc0]
+         rolw	$1, %ax, %bx
+# CHECK: roll	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd1,0xc0]
+         roll	$1, %eax, %ebx
+# CHECK: rolq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xc0]
+         rolq	$1, %rax, %rbx
+# CHECK: {nf}	rolb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xc0]
+         {nf}	rolb	$1, %al, %bl
+# CHECK: {nf}	rolw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xc0]
+         {nf}	rolw	$1, %ax, %bx
+# CHECK: {nf}	roll	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xc0]
+         {nf}	roll	$1, %eax, %ebx
+# CHECK: {nf}	rolq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xc0]
+         {nf}	rolq	$1, %rax, %rbx
+# CHECK: {evex}	rolb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0x44,0x80,0x7b]
+         {evex}	rolb	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	rolw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xd1,0x44,0x80,0x7b]
+         {evex}	rolw	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	roll	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd1,0x44,0x80,0x7b]
+         {evex}	roll	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	rolq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0x44,0x80,0x7b]
+         {evex}	rolq	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	rolb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xd0,0x44,0x80,0x7b]
+         {nf}	rolb	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	rolw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xd1,0x44,0x80,0x7b]
+         {nf}	rolw	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	roll	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xd1,0x44,0x80,0x7b]
+         {nf}	roll	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	rolq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xd1,0x44,0x80,0x7b]
+         {nf}	rolq	$1, 123(%r8,%rax,4)
+# CHECK: rolb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd0,0x44,0x80,0x7b]
+         rolb	$1, 123(%r8,%rax,4), %bl
+# CHECK: rolw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x18,0xd1,0x44,0x80,0x7b]
+         rolw	$1, 123(%r8,%rax,4), %bx
+# CHECK: roll	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd1,0x44,0x80,0x7b]
+         roll	$1, 123(%r8,%rax,4), %ebx
+# CHECK: rolq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x18,0xd1,0x44,0x80,0x7b]
+         rolq	$1, 123(%r8,%rax,4), %rbx
+# CHECK: {nf}	rolb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xd0,0x44,0x80,0x7b]
+         {nf}	rolb	$1, 123(%r8,%rax,4), %bl
+# CHECK: {nf}	rolw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x1c,0xd1,0x44,0x80,0x7b]
+         {nf}	rolw	$1, 123(%r8,%rax,4), %bx
+# CHECK: {nf}	roll	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xd1,0x44,0x80,0x7b]
+         {nf}	roll	$1, 123(%r8,%rax,4), %ebx
+# CHECK: {nf}	rolq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x1c,0xd1,0x44,0x80,0x7b]
+         {nf}	rolq	$1, 123(%r8,%rax,4), %rbx
diff --git a/llvm/test/MC/X86/apx/ror-encopt.s b/llvm/test/MC/X86/apx/ror-encopt.s
new file mode 100644
index 000000000000000..f1033a60f7d5c86
--- /dev/null
+++ b/llvm/test/MC/X86/apx/ror-encopt.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: {evex}	rorb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd0,0xc8]
+         {evex}	rorb	$1, %al
+# CHECK: {evex}	rorw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xd1,0xc8]
+         {evex}	rorw	$1, %ax
+# CHECK: {evex}	rorl	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xc8]
+         {evex}	rorl	$1, %eax
+# CHECK: {evex}	rorq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xd1,0xc8]
+         {evex}	rorq	$1, %rax
+# CHECK: {nf}	rorb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xd0,0xc8]
+         {nf}	rorb	$1, %al
+# CHECK: {nf}	rorw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xd1,0xc8]
+         {nf}	rorw	$1, %ax
+# CHECK: {nf}	rorl	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xd1,0xc8]
+         {nf}	rorl	$1, %eax
+# CHECK: {nf}	rorq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x0c,0xd1,0xc8]
+         {nf}	rorq	$1, %rax
+# CHECK: rorb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd0,0xc8]
+         rorb	$1, %al, %bl
+# CHECK: rorw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x18,0xd1,0xc8]
+         rorw	$1, %ax, %bx
+# CHECK: rorl	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd1,0xc8]
+         rorl	$1, %eax, %ebx
+# CHECK: rorq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xc8]
+         rorq	$1, %rax, %rbx
+# CHECK: {nf}	rorb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xc8]
+         {nf}	rorb	$1, %al, %bl
+# CHECK: {nf}	rorw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xc8]
+         {nf}	rorw	$1, %ax, %bx
+# CHECK: {nf}	rorl	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xc8]
+         {nf}	rorl	$1, %eax, %ebx
+# CHECK: {nf}	rorq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xc8]
+         {nf}	rorq	$1, %rax, %rbx
+# CHECK: {evex}	rorb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0x4c,0x80,0x7b]
+         {evex}	rorb	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	rorw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xd1,0x4c,0x80,0x7b]
+         {evex}	rorw	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	rorl	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd1,0x4c,0x80,0x7b]
+         {evex}	rorl	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	rorq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0x4c,0x80,0x7b]
+         {evex}	rorq	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	rorb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xd0,0x4c,0x80,0x7b]
+         {nf}	rorb	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	rorw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xd1,0x4c,0x80,0x7b]
+         {nf}	rorw	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	rorl	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xd1,0x4c,0x80,0x7b]
+         {nf}	rorl	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	rorq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xd1,0x4c,0x80,0x7b]
+         {nf}	rorq	$1, 123(%r8,%rax,4)
+# CHECK: rorb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd0,0x4c,0x80,0x7b]
+         rorb	$1, 123(%r8,%rax,4), %bl
+# CHECK: rorw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x18,0xd1,0x4c,0x80,0x7b]
+         rorw	$1, 123(%r8,%rax,4), %bx
+# CHECK: rorl	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd1,0x4c,0x80,0x7b]
+         rorl	$1, 123(%r8,%rax,4), %ebx
+# CHECK: rorq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x18,0xd1,0x4c,0x80,0x7b]
+         rorq	$1, 123(%r8,%rax,4), %rbx
+# CHECK: {nf}	rorb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xd0,0x4c,0x80,0x7b]
+         {nf}	rorb	$1, 123(%r8,%rax,4), %bl
+# CHECK: {nf}	rorw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x1c,0xd1,0x4c,0x80,0x7b]
+         {nf}	rorw	$1, 123(%r8,%rax,4), %bx
+# CHECK: {nf}	rorl	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xd1,0x4c,0x80,0x7b]
+         {nf}	rorl	$1, 123(%r8,%rax,4), %ebx
+# CHECK: {nf}	rorq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x1c,0xd1,0x4c,0x80,0x7b]
+         {nf}	rorq	$1, 123(%r8,%rax,4), %rbx
diff --git a/llvm/test/MC/X86/apx/sar-encopt.s b/llvm/test/MC/X86/apx/sar-encopt.s
new file mode 100644
index 000000000000000..1399536bf1f7ca2
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sar-encopt.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: {evex}	sarb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd0,0xf8]
+         {evex}	sarb	$1, %al
+# CHECK: {evex}	sarw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xd1,0xf8]
+         {evex}	sarw	$1, %ax
+# CHECK: {evex}	sarl	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xf8]
+         {evex}	sarl	$1, %eax
+# CHECK: {evex}	sarq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xd1,0xf8]
+         {evex}	sarq	$1, %rax
+# CHECK: {nf}	sarb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xd0,0xf8]
+         {nf}	sarb	$1, %al
+# CHECK: {nf}	sarw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xd1,0xf8]
+         {nf}	sarw	$1, %ax
+# CHECK: {nf}	sarl	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xd1,0xf8]
+         {nf}	sarl	$1, %eax
+# CHECK: {nf}	sarq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x0c,0xd1,0xf8]
+         {nf}	sarq	$1, %rax
+# CHECK: sarb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd0,0xf8]
+         sarb	$1, %al, %bl
+# CHECK: sarw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x18,0xd1,0xf8]
+         sarw	$1, %ax, %bx
+# CHECK: sarl	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd1,0xf8]
+         sarl	$1, %eax, %ebx
+# CHECK: sarq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xf8]
+         sarq	$1, %rax, %rbx
+# CHECK: {nf}	sarb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xf8]
+         {nf}	sarb	$1, %al, %bl
+# CHECK: {nf}	sarw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xf8]
+         {nf}	sarw	$1, %ax, %bx
+# CHECK: {nf}	sarl	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xf8]
+         {nf}	sarl	$1, %eax, %ebx
+# CHECK: {nf}	sarq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xf8]
+         {nf}	sarq	$1, %rax, %rbx
+# CHECK: {evex}	sarb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0x7c,0x80,0x7b]
+         {evex}	sarb	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	sarw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xd1,0x7c,0x80,0x7b]
+         {evex}	sarw	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	sarl	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd1,0x7c,0x80,0x7b]
+         {evex}	sarl	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	sarq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0x7c,0x80,0x7b]
+         {evex}	sarq	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	sarb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xd0,0x7c,0x80,0x7b]
+         {nf}	sarb	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	sarw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xd1,0x7c,0x80,0x7b]
+         {nf}	sarw	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	sarl	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xd1,0x7c,0x80,0x7b]
+         {nf}	sarl	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	sarq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xd1,0x7c,0x80,0x7b]
+         {nf}	sarq	$1, 123(%r8,%rax,4)
+# CHECK: sarb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd0,0x7c,0x80,0x7b]
+         sarb	$1, 123(%r8,%rax,4), %bl
+# CHECK: sarw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x18,0xd1,0x7c,0x80,0x7b]
+         sarw	$1, 123(%r8,%rax,4), %bx
+# CHECK: sarl	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd1,0x7c,0x80,0x7b]
+         sarl	$1, 123(%r8,%rax,4), %ebx
+# CHECK: sarq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x18,0xd1,0x7c,0x80,0x7b]
+         sarq	$1, 123(%r8,%rax,4), %rbx
+# CHECK: {nf}	sarb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xd0,0x7c,0x80,0x7b]
+         {nf}	sarb	$1, 123(%r8,%rax,4), %bl
+# CHECK: {nf}	sarw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x1c,0xd1,0x7c,0x80,0x7b]
+         {nf}	sarw	$1, 123(%r8,%rax,4), %bx
+# CHECK: {nf}	sarl	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xd1,0x7c,0x80,0x7b]
+         {nf}	sarl	$1, 123(%r8,%rax,4), %ebx
+# CHECK: {nf}	sarq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x1c,0xd1,0x7c,0x80,0x7b]
+         {nf}	sarq	$1, 123(%r8,%rax,4), %rbx
diff --git a/llvm/test/MC/X86/apx/sbb-reloc.s b/llvm/test/MC/X86/apx/sbb-reloc.s
new file mode 100644
index 000000000000000..29812ec63195b42
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sbb-reloc.s
@@ -0,0 +1,22 @@
+// RUN: llvm-mc -triple x86_64-linux-gnu -filetype=obj %s | llvm-readobj -r - | FileCheck %s
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section ({{[0-9]+}}) .rela.text {
+{evex}  sbbb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+sbbb $foo, %al, %bl                         // CHECK-NEXT:     R_X86_64_8
+{evex}  sbbb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8   
+sbbb $foo, 123(%r8,%rax,4), %bl             // CHECK-NEXT:     R_X86_64_8
+{evex}  sbbw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+sbbw $foo, %ax, %bx                         // CHECK-NEXT:     R_X86_64_16
+{evex}  sbbw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+sbbw $foo, 123(%r8,%rax,4), %bx             // CHECK-NEXT:     R_X86_64_16
+{evex}  sbbl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+sbbl $foo, %eax, %ebx                       // CHECK-NEXT:     R_X86_64_32
+{evex}  sbbl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+sbbl $foo, 123(%r8,%rax,4), %ebx            // CHECK-NEXT:     R_X86_64_32
+{evex}  sbbq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+sbbq $foo, %rax, %rbx                       // CHECK-NEXT:     R_X86_64_32S
+{evex}  sbbq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+sbbq $foo, 123(%r8,%rax,4), %rbx            // CHECK-NEXT:     R_X86_64_32S
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
diff --git a/llvm/test/MC/X86/apx/shl-encopt.s b/llvm/test/MC/X86/apx/shl-encopt.s
new file mode 100644
index 000000000000000..0feeddc14006419
--- /dev/null
+++ b/llvm/test/MC/X86/apx/shl-encopt.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: {evex}	shlb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd0,0xe0]
+         {evex}	shlb	$1, %al
+# CHECK: {evex}	shlw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xd1,0xe0]
+         {evex}	shlw	$1, %ax
+# CHECK: {evex}	shll	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xe0]
+         {evex}	shll	$1, %eax
+# CHECK: {evex}	shlq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xd1,0xe0]
+         {evex}	shlq	$1, %rax
+# CHECK: {nf}	shlb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xd0,0xe0]
+         {nf}	shlb	$1, %al
+# CHECK: {nf}	shlw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xd1,0xe0]
+         {nf}	shlw	$1, %ax
+# CHECK: {nf}	shll	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xd1,0xe0]
+         {nf}	shll	$1, %eax
+# CHECK: {nf}	shlq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x0c,0xd1,0xe0]
+         {nf}	shlq	$1, %rax
+# CHECK: shlb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd0,0xe0]
+         shlb	$1, %al, %bl
+# CHECK: shlw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x18,0xd1,0xe0]
+         shlw	$1, %ax, %bx
+# CHECK: shll	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd1,0xe0]
+         shll	%eax, %ebx
+# CHECK: shlq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xe0]
+         shlq	$1, %rax, %rbx
+# CHECK: {nf}	shlb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xe0]
+         {nf}	shlb	$1, %al, %bl
+# CHECK: {nf}	shlw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xe0]
+         {nf}	shlw	$1, %ax, %bx
+# CHECK: {nf}	shll	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xe0]
+         {nf}	shll	$1, %eax, %ebx
+# CHECK: {nf}	shlq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xe0]
+         {nf}	shlq	$1, %rax, %rbx
+# CHECK: {evex}	shlb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0x64,0x80,0x7b]
+         {evex}	shlb	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	shlw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xd1,0x64,0x80,0x7b]
+         {evex}	shlw	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	shll	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd1,0x64,0x80,0x7b]
+         {evex}	shll	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	shlq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0x64,0x80,0x7b]
+         {evex}	shlq	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	shlb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xd0,0x64,0x80,0x7b]
+         {nf}	shlb	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	shlw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xd1,0x64,0x80,0x7b]
+         {nf}	shlw	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	shll	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xd1,0x64,0x80,0x7b]
+         {nf}	shll	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	shlq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xd1,0x64,0x80,0x7b]
+         {nf}	shlq	$1, 123(%r8,%rax,4)
+# CHECK: shlb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd0,0x64,0x80,0x7b]
+         shlb	$1, 123(%r8,%rax,4), %bl
+# CHECK: shlw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x18,0xd1,0x64,0x80,0x7b]
+         shlw	$1, 123(%r8,%rax,4), %bx
+# CHECK: shll	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd1,0x64,0x80,0x7b]
+         shll	$1, 123(%r8,%rax,4), %ebx
+# CHECK: shlq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x18,0xd1,0x64,0x80,0x7b]
+         shlq	$1, 123(%r8,%rax,4), %rbx
+# CHECK: {nf}	shlb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xd0,0x64,0x80,0x7b]
+         {nf}	shlb	$1, 123(%r8,%rax,4), %bl
+# CHECK: {nf}	shlw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x1c,0xd1,0x64,0x80,0x7b]
+         {nf}	shlw	$1, 123(%r8,%rax,4), %bx
+# CHECK: {nf}	shll	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xd1,0x64,0x80,0x7b]
+         {nf}	shll	$1, 123(%r8,%rax,4), %ebx
+# CHECK: {nf}	shlq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x1c,0xd1,0x64,0x80,0x7b]
+         {nf}	shlq	$1, 123(%r8,%rax,4), %rbx
diff --git a/llvm/test/MC/X86/apx/shr-encopt.s b/llvm/test/MC/X86/apx/shr-encopt.s
new file mode 100644
index 000000000000000..97b6b700865737f
--- /dev/null
+++ b/llvm/test/MC/X86/apx/shr-encopt.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: {evex}	shrb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd0,0xe8]
+         {evex}	shrb	$1, %al
+# CHECK: {evex}	shrw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xd1,0xe8]
+         {evex}	shrw	$1, %ax
+# CHECK: {evex}	shrl	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xe8]
+         {evex}	shrl	$1, %eax
+# CHECK: {evex}	shrq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xd1,0xe8]
+         {evex}	shrq	$1, %rax
+# CHECK: {nf}	shrb	%al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xd0,0xe8]
+         {nf}	shrb	$1, %al
+# CHECK: {nf}	shrw	%ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xd1,0xe8]
+         {nf}	shrw	$1, %ax
+# CHECK: {nf}	shrl	%eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xd1,0xe8]
+         {nf}	shrl	$1, %eax
+# CHECK: {nf}	shrq	%rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x0c,0xd1,0xe8]
+         {nf}	shrq	$1, %rax
+# CHECK: shrb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd0,0xe8]
+         shrb	$1, %al, %bl
+# CHECK: shrw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x18,0xd1,0xe8]
+         shrw	$1, %ax, %bx
+# CHECK: shrl	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xd1,0xe8]
+         shrl	$1, %eax, %ebx
+# CHECK: shrq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xe8]
+         shrq	$1, %rax, %rbx
+# CHECK: {nf}	shrb	%al, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xe8]
+         {nf}	shrb	$1, %al, %bl
+# CHECK: {nf}	shrw	%ax, %bx
+# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xe8]
+         {nf}	shrw	$1, %ax, %bx
+# CHECK: {nf}	shrl	%eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xe8]
+         {nf}	shrl	$1, %eax, %ebx
+# CHECK: {nf}	shrq	%rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xe8]
+         {nf}	shrq	$1, %rax, %rbx
+# CHECK: {evex}	shrb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0x6c,0x80,0x7b]
+         {evex}	shrb	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	shrw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xd1,0x6c,0x80,0x7b]
+         {evex}	shrw	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	shrl	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd1,0x6c,0x80,0x7b]
+         {evex}	shrl	$1, 123(%r8,%rax,4)
+# CHECK: {evex}	shrq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0x6c,0x80,0x7b]
+         {evex}	shrq	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	shrb	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xd0,0x6c,0x80,0x7b]
+         {nf}	shrb	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	shrw	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xd1,0x6c,0x80,0x7b]
+         {nf}	shrw	123(%r8,%rax,4)
+# CHECK: {nf}	shrl	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xd1,0x6c,0x80,0x7b]
+         {nf}	shrl	$1, 123(%r8,%rax,4)
+# CHECK: {nf}	shrq	123(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xd1,0x6c,0x80,0x7b]
+         {nf}	shrq	$1, 123(%r8,%rax,4)
+# CHECK: shrb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd0,0x6c,0x80,0x7b]
+         shrb	$1, 123(%r8,%rax,4), %bl
+# CHECK: shrw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x18,0xd1,0x6c,0x80,0x7b]
+         shrw	$1, 123(%r8,%rax,4), %bx
+# CHECK: shrl	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xd1,0x6c,0x80,0x7b]
+         shrl	$1, 123(%r8,%rax,4), %ebx
+# CHECK: shrq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x18,0xd1,0x6c,0x80,0x7b]
+         shrq	$1, 123(%r8,%rax,4), %rbx
+# CHECK: {nf}	shrb	123(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xd0,0x6c,0x80,0x7b]
+         {nf}	shrb	$1, 123(%r8,%rax,4), %bl
+# CHECK: {nf}	shrw	123(%r8,%rax,4), %bx
+# CHECK: encoding: [0x62,0xd4,0x65,0x1c,0xd1,0x6c,0x80,0x7b]
+         {nf}	shrw	$1, 123(%r8,%rax,4), %bx
+# CHECK: {nf}	shrl	123(%r8,%rax,4), %ebx
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xd1,0x6c,0x80,0x7b]
+         {nf}	shrl	$1, 123(%r8,%rax,4), %ebx
+# CHECK: {nf}	shrq	123(%r8,%rax,4), %rbx
+# CHECK: encoding: [0x62,0xd4,0xe4,0x1c,0xd1,0x6c,0x80,0x7b]
+         {nf}	shrq	$1, 123(%r8,%rax,4), %rbx
diff --git a/llvm/test/MC/X86/apx/sub-reloc.s b/llvm/test/MC/X86/apx/sub-reloc.s
new file mode 100644
index 000000000000000..0f8f689e4eb12db
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sub-reloc.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple x86_64-linux-gnu -filetype=obj %s | llvm-readobj -r - | FileCheck %s
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section ({{[0-9]+}}) .rela.text {
+{evex}  subb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+{nf}    subb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+subb $foo, %al, %bl                         // CHECK-NEXT:     R_X86_64_8
+{nf}    subb $foo, %al, %bl                 // CHECK-NEXT:     R_X86_64_8
+{evex}  subb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8   
+{nf}    subb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8
+subb $foo, 123(%r8,%rax,4), %bl             // CHECK-NEXT:     R_X86_64_8
+{nf}    subb $foo, 123(%r8,%rax,4), %bl     // CHECK-NEXT:     R_X86_64_8
+{evex}  subw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+{nf}    subw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+subw $foo, %ax, %bx                         // CHECK-NEXT:     R_X86_64_16
+{nf}    subw $foo, %ax, %bx                 // CHECK-NEXT:     R_X86_64_16
+{evex}  subw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+{nf}    subw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+subw $foo, 123(%r8,%rax,4), %bx             // CHECK-NEXT:     R_X86_64_16
+{nf}    subw $foo, 123(%r8,%rax,4), %bx     // CHECK-NEXT:     R_X86_64_16
+{evex}  subl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+{nf}    subl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+subl $foo, %eax, %ebx                       // CHECK-NEXT:     R_X86_64_32
+{nf}    subl $foo, %eax, %ebx               // CHECK-NEXT:     R_X86_64_32
+{evex}  subl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+{nf}    subl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+subl $foo, 123(%r8,%rax,4), %ebx            // CHECK-NEXT:     R_X86_64_32
+{nf}    subl $foo, 123(%r8,%rax,4), %ebx    // CHECK-NEXT:     R_X86_64_32
+{evex}  subq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+{nf}    subq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+subq $foo, %rax, %rbx                       // CHECK-NEXT:     R_X86_64_32S
+{nf}    subq $foo, %rax, %rbx               // CHECK-NEXT:     R_X86_64_32S
+{evex}  subq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+{nf}    subq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+subq $foo, 123(%r8,%rax,4), %rbx            // CHECK-NEXT:     R_X86_64_32S
+{nf}    subq $foo, 123(%r8,%rax,4), %rbx    // CHECK-NEXT:     R_X86_64_32S
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
diff --git a/llvm/test/MC/X86/apx/xor-reloc.s b/llvm/test/MC/X86/apx/xor-reloc.s
new file mode 100644
index 000000000000000..f4199657775fb39
--- /dev/null
+++ b/llvm/test/MC/X86/apx/xor-reloc.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple x86_64-linux-gnu -filetype=obj %s | llvm-readobj -r - | FileCheck %s
+
+// CHECK:      Relocations [
+// CHECK-NEXT:   Section ({{[0-9]+}}) .rela.text {
+{evex}  xorb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+{nf}    xorb $foo, %al                      // CHECK-NEXT:     R_X86_64_8
+xorb $foo, %al, %bl                         // CHECK-NEXT:     R_X86_64_8
+{nf}    xorb $foo, %al, %bl                 // CHECK-NEXT:     R_X86_64_8
+{evex}  xorb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8   
+{nf}    xorb $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_8
+xorb $foo, 123(%r8,%rax,4), %bl             // CHECK-NEXT:     R_X86_64_8
+{nf}    xorb $foo, 123(%r8,%rax,4), %bl     // CHECK-NEXT:     R_X86_64_8
+{evex}  xorw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+{nf}    xorw $foo, %ax                      // CHECK-NEXT:     R_X86_64_16
+xorw $foo, %ax, %bx                         // CHECK-NEXT:     R_X86_64_16
+{nf}    xorw $foo, %ax, %bx                 // CHECK-NEXT:     R_X86_64_16
+{evex}  xorw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+{nf}    xorw $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_16
+xorw $foo, 123(%r8,%rax,4), %bx             // CHECK-NEXT:     R_X86_64_16
+{nf}    xorw $foo, 123(%r8,%rax,4), %bx     // CHECK-NEXT:     R_X86_64_16
+{evex}  xorl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+{nf}    xorl $foo, %eax                     // CHECK-NEXT:     R_X86_64_32
+xorl $foo, %eax, %ebx                       // CHECK-NEXT:     R_X86_64_32
+{nf}    xorl $foo, %eax, %ebx               // CHECK-NEXT:     R_X86_64_32
+{evex}  xorl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+{nf}    xorl $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32
+xorl $foo, 123(%r8,%rax,4), %ebx            // CHECK-NEXT:     R_X86_64_32
+{nf}    xorl $foo, 123(%r8,%rax,4), %ebx    // CHECK-NEXT:     R_X86_64_32
+{evex}  xorq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+{nf}    xorq $foo, %rax                     // CHECK-NEXT:     R_X86_64_32S
+xorq $foo, %rax, %rbx                       // CHECK-NEXT:     R_X86_64_32S
+{nf}    xorq $foo, %rax, %rbx               // CHECK-NEXT:     R_X86_64_32S
+{evex}  xorq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+{nf}    xorq $foo, 123(%r8,%rax,4)          // CHECK-NEXT:     R_X86_64_32S
+xorq $foo, 123(%r8,%rax,4), %rbx            // CHECK-NEXT:     R_X86_64_32S
+{nf}    xorq $foo, 123(%r8,%rax,4), %rbx    // CHECK-NEXT:     R_X86_64_32S
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]



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