[llvm] [AMDGPU][NFC] Rename the reg-or-imm operand predicates to match their class names. (PR #79439)
Mariusz Sikora via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 26 00:47:20 PST 2024
================
@@ -451,45 +451,39 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64);
}
- bool isSSrcB32() const {
- return isSCSrcB32() || isLiteralImm(MVT::i32) || isExpr();
+ bool isSSrc_b32() const {
+ return isSCSrc_b32() || isLiteralImm(MVT::i32) || isExpr();
}
- bool isSSrcB16() const {
- return isSCSrcB16() || isLiteralImm(MVT::i16);
- }
+ bool isSSrc_b16() const { return isSCSrcB16() || isLiteralImm(MVT::i16); }
bool isSSrcV2B16() const {
llvm_unreachable("cannot happen");
- return isSSrcB16();
+ return isSSrc_b16();
}
- bool isSSrcB64() const {
+ bool isSSrc_b64() const {
// TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.
// See isVSrc64().
- return isSCSrcB64() || isLiteralImm(MVT::i64);
+ return isSCSrc_b64() || isLiteralImm(MVT::i64);
}
- bool isSSrcF32() const {
- return isSCSrcB32() || isLiteralImm(MVT::f32) || isExpr();
+ bool isSSrc_f32() const {
+ return isSCSrc_b32() || isLiteralImm(MVT::f32) || isExpr();
}
- bool isSSrcF64() const {
- return isSCSrcB64() || isLiteralImm(MVT::f64);
- }
+ bool isSSrcF64() const { return isSCSrc_b64() || isLiteralImm(MVT::f64); }
----------------
mariusz-sikora-at-amd wrote:
Why this was not changed to `isSSrc_f64` and some other like `isVISrcB32` ?
https://github.com/llvm/llvm-project/pull/79439
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