[llvm] f0012dc - [AArch64] Add a couple more csinc tests with disjoint ors. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2024-01-26T08:30:35Z
New Revision: f0012dcce4c08d0e4a16b65f2a15f7dc7fb7e533

URL: https://github.com/llvm/llvm-project/commit/f0012dcce4c08d0e4a16b65f2a15f7dc7fb7e533
DIFF: https://github.com/llvm/llvm-project/commit/f0012dcce4c08d0e4a16b65f2a15f7dc7fb7e533.diff

LOG: [AArch64] Add a couple more csinc tests with disjoint ors. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/arm64-csel.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/arm64-csel.ll b/llvm/test/CodeGen/AArch64/arm64-csel.ll
index bda0c6509101472..05950f1f51e257c 100644
--- a/llvm/test/CodeGen/AArch64/arm64-csel.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-csel.ll
@@ -468,6 +468,21 @@ entry:
   ret i32 %sel
 }
 
+define i32 @selor32_2(i32 %num, i32 %x) {
+; CHECK-LABEL: selor32_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    and w8, w0, #0xff00
+; CHECK-NEXT:    cmp w1, #0
+; CHECK-NEXT:    orr w9, w8, #0x2
+; CHECK-NEXT:    csel w0, w9, w8, ne
+; CHECK-NEXT:    ret
+entry:
+  %and = and i32 %num, 65280
+  %tobool.not = icmp ne i32 %x, 0
+  %or = or disjoint i32 %and, 2
+  %sel = select i1 %tobool.not, i32 %or, i32 %and
+  ret i32 %sel
+}
 
 define i64 @selor64(i64 %num, i64 %x) {
 ; CHECK-LABEL: selor64:
@@ -484,3 +499,18 @@ entry:
   %sel = select i1 %tobool.not, i64 %or, i64 %and
   ret i64 %sel
 }
+
+; Same as above with disjoint but without knowing haveNoCommonBitsSet.
+define i64 @selor64_disjoint(i64 %num, i64 %x) {
+; CHECK-LABEL: selor64_disjoint:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    orr x8, x0, #0x1
+; CHECK-NEXT:    cmp x1, #0
+; CHECK-NEXT:    csel x0, x8, x0, ne
+; CHECK-NEXT:    ret
+entry:
+  %tobool.not = icmp ne i64 %x, 0
+  %or = or disjoint i64 %num, 1
+  %sel = select i1 %tobool.not, i64 %or, i64 %num
+  ret i64 %sel
+}