[llvm] 6d0080b - [X86] Support promoted ENQCMD, KEYLOCKER and USERMSR (#77293)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 25 22:24:48 PST 2024
Author: XinWang10
Date: 2024-01-26T14:24:43+08:00
New Revision: 6d0080b5de26d8a8682ec6169851af3d04e30ccb
URL: https://github.com/llvm/llvm-project/commit/6d0080b5de26d8a8682ec6169851af3d04e30ccb
DIFF: https://github.com/llvm/llvm-project/commit/6d0080b5de26d8a8682ec6169851af3d04e30ccb.diff
LOG: [X86] Support promoted ENQCMD, KEYLOCKER and USERMSR (#77293)
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the promoted ENQCMD, KEYLOCKER and USER-MSR
instructions in EVEX space.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
Added:
llvm/test/MC/Disassembler/X86/apx/enqcmd.txt
llvm/test/MC/Disassembler/X86/apx/keylocker.txt
llvm/test/MC/Disassembler/X86/apx/user-msr.txt
llvm/test/MC/X86/apx/enqcmd-att.s
llvm/test/MC/X86/apx/enqcmd-intel.s
llvm/test/MC/X86/apx/keylocker-att.s
llvm/test/MC/X86/apx/keylocker-intel.s
llvm/test/MC/X86/apx/user-msr-att.s
llvm/test/MC/X86/apx/user-msr-intel.s
Modified:
llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86InstrKL.td
llvm/lib/Target/X86/X86InstrMisc.td
llvm/lib/Target/X86/X86InstrSystem.td
llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
llvm/test/CodeGen/X86/usermsr-intrinsics.ll
llvm/utils/TableGen/X86DisassemblerTables.cpp
llvm/utils/TableGen/X86RecognizableInstr.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
index 3aceb247a26c21..0dc974ea9efd8d 100644
--- a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
+++ b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
@@ -140,7 +140,9 @@ enum attributeBits {
ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
ENUM_ENTRY(IC_EVEX_NF, 2, "requires EVEX and NF prefix") \
ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
+ ENUM_ENTRY(IC_EVEX_XS_ADSIZE, 3, "requires EVEX, XS and the ADSIZE prefix") \
ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
+ ENUM_ENTRY(IC_EVEX_XD_ADSIZE, 3, "requires EVEX, XD and the ADSIZE prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_NF, 3, "requires EVEX, NF and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_ADSIZE, 3, \
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index ce7f707066bb07..5f852613610664 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -941,6 +941,9 @@ static bool readOpcode(struct InternalInstruction *insn) {
case VEX_LOB_MAP6:
insn->opcodeType = MAP6;
return consume(insn, insn->opcode);
+ case VEX_LOB_MAP7:
+ insn->opcodeType = MAP7;
+ return consume(insn, insn->opcode);
}
} else if (insn->vectorExtensionType == TYPE_VEX_3B) {
switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 833f058253d880..c0b7a5523b5d8f 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5035,14 +5035,18 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
unsigned Opcode;
switch (IntNo) {
default: llvm_unreachable("Impossible intrinsic");
- case Intrinsic::x86_encodekey128: Opcode = X86::ENCODEKEY128; break;
- case Intrinsic::x86_encodekey256: Opcode = X86::ENCODEKEY256; break;
+ case Intrinsic::x86_encodekey128:
+ Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY128);
+ break;
+ case Intrinsic::x86_encodekey256:
+ Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY256);
+ break;
}
SDValue Chain = Node->getOperand(0);
Chain = CurDAG->getCopyToReg(Chain, dl, X86::XMM0, Node->getOperand(3),
SDValue());
- if (Opcode == X86::ENCODEKEY256)
+ if (Opcode == X86::ENCODEKEY256 || Opcode == X86::ENCODEKEY256_EVEX)
Chain = CurDAG->getCopyToReg(Chain, dl, X86::XMM1, Node->getOperand(4),
Chain.getValue(1));
@@ -5514,7 +5518,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
LoReg = UseMULX ? X86::RDX : X86::RAX;
HiReg = X86::RDX;
break;
-#undef GET_EGPR_IF_ENABLED
}
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
@@ -6394,17 +6397,18 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
default:
llvm_unreachable("Unexpected opcode!");
case X86ISD::AESENCWIDE128KL:
- Opcode = X86::AESENCWIDE128KL;
+ Opcode = GET_EGPR_IF_ENABLED(X86::AESENCWIDE128KL);
break;
case X86ISD::AESDECWIDE128KL:
- Opcode = X86::AESDECWIDE128KL;
+ Opcode = GET_EGPR_IF_ENABLED(X86::AESDECWIDE128KL);
break;
case X86ISD::AESENCWIDE256KL:
- Opcode = X86::AESENCWIDE256KL;
+ Opcode = GET_EGPR_IF_ENABLED(X86::AESENCWIDE256KL);
break;
case X86ISD::AESDECWIDE256KL:
- Opcode = X86::AESDECWIDE256KL;
+ Opcode = GET_EGPR_IF_ENABLED(X86::AESDECWIDE256KL);
break;
+#undef GET_EGPR_IF_ENABLED
}
SDValue Chain = Node->getOperand(0);
diff --git a/llvm/lib/Target/X86/X86InstrKL.td b/llvm/lib/Target/X86/X86InstrKL.td
index 4586fc541627fe..32423e08ed4c53 100644
--- a/llvm/lib/Target/X86/X86InstrKL.td
+++ b/llvm/lib/Target/X86/X86InstrKL.td
@@ -14,61 +14,75 @@
//===----------------------------------------------------------------------===//
// Key Locker instructions
+class Encodekey<bits<8> opcode, string m>
+ : I<opcode, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), m#"\t{$src, $dst|$dst, $src}", []>,
+ NoCD8, XS;
-let SchedRW = [WriteSystem], Predicates = [HasKL] in {
- let Uses = [XMM0, EAX], Defs = [EFLAGS] in {
+multiclass Aesencdec<string suffix> {
+ def AESENC128KL#suffix : I<0xDC, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, opaquemem:$src2),
+ "aesenc128kl\t{$src2, $src1|$src1, $src2}",
+ [(set VR128:$dst, EFLAGS, (X86aesenc128kl VR128:$src1, addr:$src2))]>,
+ NoCD8, XS;
+ def AESDEC128KL#suffix : I<0xDD, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, opaquemem:$src2),
+ "aesdec128kl\t{$src2, $src1|$src1, $src2}",
+ [(set VR128:$dst, EFLAGS, (X86aesdec128kl VR128:$src1, addr:$src2))]>,
+ NoCD8, XS;
+ def AESENC256KL#suffix : I<0xDE, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, opaquemem:$src2),
+ "aesenc256kl\t{$src2, $src1|$src1, $src2}",
+ [(set VR128:$dst, EFLAGS, (X86aesenc256kl VR128:$src1, addr:$src2))]>,
+ NoCD8, XS;
+ def AESDEC256KL#suffix : I<0xDF, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, opaquemem:$src2),
+ "aesdec256kl\t{$src2, $src1|$src1, $src2}",
+ [(set VR128:$dst, EFLAGS, (X86aesdec256kl VR128:$src1, addr:$src2))]>,
+ NoCD8, XS;
+}
+
+let SchedRW = [WriteSystem] in {
+ let Uses = [XMM0, EAX], Defs = [EFLAGS], Predicates = [HasKL] in {
def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
"loadiwkey\t{$src2, $src1|$src1, $src2}",
[(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8, XS;
}
- let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
- def ENCODEKEY128 : I<0xFA, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
- "encodekey128\t{$src, $dst|$dst, $src}", []>, T8, XS;
- }
+ let Predicates = [HasKL, NoEGPR] in {
+ let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in
+ def ENCODEKEY128 : Encodekey<0xFA, "encodekey128">, T8;
- let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
- def ENCODEKEY256 : I<0xFB, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
- "encodekey256\t{$src, $dst|$dst, $src}", []>, T8, XS;
- }
+ let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
+ def ENCODEKEY256 : Encodekey<0xFB, "encodekey256">, T8;
- let Constraints = "$src1 = $dst",
- Defs = [EFLAGS] in {
- def AESENC128KL : I<0xDC, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
- "aesenc128kl\t{$src2, $src1|$src1, $src2}",
- [(set VR128:$dst, EFLAGS,
- (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8, XS;
+ let Constraints = "$src1 = $dst", Defs = [EFLAGS] in
+ defm "" : Aesencdec<"">, T8;
+ }
- def AESDEC128KL : I<0xDD, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
- "aesdec128kl\t{$src2, $src1|$src1, $src2}",
- [(set VR128:$dst, EFLAGS,
- (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8, XS;
+ let Predicates = [HasKL, HasEGPR, In64BitMode] in {
+ let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in
+ def ENCODEKEY128_EVEX : Encodekey<0xDA, "encodekey128">, EVEX, T_MAP4;
- def AESENC256KL : I<0xDE, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
- "aesenc256kl\t{$src2, $src1|$src1, $src2}",
- [(set VR128:$dst, EFLAGS,
- (X86aesenc256kl VR128:$src1, addr:$src2))]>, T8, XS;
+ let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
+ def ENCODEKEY256_EVEX : Encodekey<0xDB, "encodekey256">, EVEX, T_MAP4;
- def AESDEC256KL : I<0xDF, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
- "aesdec256kl\t{$src2, $src1|$src1, $src2}",
- [(set VR128:$dst, EFLAGS,
- (X86aesdec256kl VR128:$src1, addr:$src2))]>, T8, XS;
+ let Constraints = "$src1 = $dst", Defs = [EFLAGS] in
+ defm "" : Aesencdec<"_EVEX">, EVEX, T_MAP4;
}
+} // SchedRW
-} // SchedRW, Predicates
+multiclass Aesencdecwide<string suffix> {
+ def AESENCWIDE128KL#suffix : I<0xD8, MRM0m, (outs), (ins opaquemem:$src), "aesencwide128kl\t$src", []>, NoCD8, XS;
+ def AESDECWIDE128KL#suffix : I<0xD8, MRM1m, (outs), (ins opaquemem:$src), "aesdecwide128kl\t$src", []>, NoCD8, XS;
+ def AESENCWIDE256KL#suffix : I<0xD8, MRM2m, (outs), (ins opaquemem:$src), "aesencwide256kl\t$src", []>, NoCD8, XS;
+ def AESDECWIDE256KL#suffix : I<0xD8, MRM3m, (outs), (ins opaquemem:$src), "aesdecwide256kl\t$src", []>, NoCD8, XS;
+}
-let SchedRW = [WriteSystem], Predicates = [HasWIDEKL] in {
- let Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
- Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
- mayLoad = 1 in {
- def AESENCWIDE128KL : I<0xD8, MRM0m, (outs), (ins opaquemem:$src),
- "aesencwide128kl\t$src", []>, T8, XS;
- def AESDECWIDE128KL : I<0xD8, MRM1m, (outs), (ins opaquemem:$src),
- "aesdecwide128kl\t$src", []>, T8, XS;
- def AESENCWIDE256KL : I<0xD8, MRM2m, (outs), (ins opaquemem:$src),
- "aesencwide256kl\t$src", []>, T8, XS;
- def AESDECWIDE256KL : I<0xD8, MRM3m, (outs), (ins opaquemem:$src),
- "aesdecwide256kl\t$src", []>, T8, XS;
- }
+let SchedRW = [WriteSystem], Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
+ Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], mayLoad = 1 in {
+ let Predicates = [HasWIDEKL, NoEGPR] in
+ defm "" : Aesencdecwide<"">, T8;
-} // SchedRW, Predicates
+ let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in
+ defm "" : Aesencdecwide<"_EVEX">, EVEX, T_MAP4;
+} // SchedRW
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
index 66fac2369d0a91..c8e8d3f3ed5800 100644
--- a/llvm/lib/Target/X86/X86InstrMisc.td
+++ b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -1557,32 +1557,39 @@ def MOVDIR64B64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$
//===----------------------------------------------------------------------===//
// ENQCMD/S - Enqueue 64-byte command as user with 64-byte write atomicity
//
+multiclass Enqcmds<string suffix> {
+ def ENQCMD32#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
+ "enqcmd\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
+ NoCD8, XD, AdSize32;
+ def ENQCMD64#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
+ "enqcmd\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
+ NoCD8, XD, AdSize64;
+
+ def ENQCMDS32#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
+ "enqcmds\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
+ NoCD8, XS, AdSize32;
+ def ENQCMDS64#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
+ "enqcmds\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
+ NoCD8, XS, AdSize64;
+}
+
let SchedRW = [WriteStore], Defs = [EFLAGS] in {
def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
- "enqcmd\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>,
+ "enqcmd\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>,
T8, XD, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
- def ENQCMD32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
- "enqcmd\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
- T8, XD, AdSize32, Requires<[HasENQCMD]>;
- def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
- "enqcmd\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
- T8, XD, AdSize64, Requires<[HasENQCMD, In64BitMode]>;
-
def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
- "enqcmds\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>,
- T8, XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
- def ENQCMDS32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
- "enqcmds\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
- T8, XS, AdSize32, Requires<[HasENQCMD]>;
- def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
- "enqcmds\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
- T8, XS, AdSize64, Requires<[HasENQCMD, In64BitMode]>;
+ "enqcmds\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>,
+ T8, XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
+
+ defm "" : Enqcmds<"">, T8, Requires<[HasENQCMD, NoEGPR]>;
+ defm "" : Enqcmds<"_EVEX">, EVEX, T_MAP4, Requires<[HasENQCMD, HasEGPR, In64BitMode]>;
+
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index b1be4739617dfc..a7899a2492b882 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -436,22 +436,35 @@ def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
}
-let Predicates = [HasUSERMSR], mayLoad = 1 in {
- def URDMSRrr : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
- "urdmsr\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T8, XD;
- def URDMSRri : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
- "urdmsr\t{$imm, $dst|$dst, $imm}",
- [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, VEX;
+multiclass Urdwrmsr<Map rrmap, string suffix> {
+ let mayLoad = 1 in {
+ let OpMap = rrmap in
+ def URDMSRrr#suffix : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
+ "urdmsr\t{$src, $dst|$dst, $src}",
+ [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, XD, NoCD8;
+ def URDMSRri#suffix : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
+ "urdmsr\t{$imm, $dst|$dst, $imm}",
+ [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>,
+ T_MAP7, VEX, XD, NoCD8;
}
-let Predicates = [HasUSERMSR], mayStore = 1 in {
- def UWRMSRrr : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
- "uwrmsr\t{$src2, $src1|$src1, $src2}",
- [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T8, XS;
- def UWRMSRir : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
- "uwrmsr\t{$src, $imm|$imm, $src}",
- [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, VEX;
+ let mayStore = 1 in {
+ let OpMap = rrmap in
+ def UWRMSRrr#suffix : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
+ "uwrmsr\t{$src2, $src1|$src1, $src2}",
+ [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, XS, NoCD8;
+ def UWRMSRir#suffix : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
+ "uwrmsr\t{$src, $imm|$imm, $src}",
+ [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>,
+ T_MAP7, VEX, XS, NoCD8;
+ }
}
+
+let Predicates = [HasUSERMSR, NoEGPR] in
+ defm "" : Urdwrmsr<T8, "">;
+
+let Predicates = [HasUSERMSR, HasEGPR, In64BitMode] in
+ defm "" : Urdwrmsr<T_MAP4, "_EVEX">, EVEX;
+
let Defs = [RAX, RDX], Uses = [ECX] in
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
diff --git a/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll b/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
index e5a6d2ead72d36..0b09c8fc1e74e6 100644
--- a/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
@@ -2,6 +2,7 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+enqcmd | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+enqcmd | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+enqcmd | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+enqcmd,+egpr --show-mc-encoding | FileCheck %s --check-prefix=EGPR
define i8 @test_enqcmd(ptr %dst, ptr %src) {
; X64-LABEL: test_enqcmd:
@@ -23,6 +24,12 @@ define i8 @test_enqcmd(ptr %dst, ptr %src) {
; X32-NEXT: enqcmd (%esi), %edi
; X32-NEXT: sete %al
; X32-NEXT: retq
+;
+; EGPR-LABEL: test_enqcmd:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: enqcmd (%rsi), %rdi # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf8,0x3e]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
@@ -50,6 +57,12 @@ define i8 @test_enqcmds(ptr %dst, ptr %src) {
; X32-NEXT: enqcmds (%esi), %edi
; X32-NEXT: sete %al
; X32-NEXT: retq
+;
+; EGPR-LABEL: test_enqcmds:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: enqcmds (%rsi), %rdi # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xf8,0x3e]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
diff --git a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
index 78eecdaf29e2cb..ae046be9a50832 100644
--- a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+kl,+widekl | FileCheck %s
+; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+kl,+widekl,+egpr --show-mc-encoding | FileCheck %s --check-prefix=EGPR
; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/X86/keylocker-builtins.c
@@ -9,6 +10,12 @@ define void @test_loadiwkey(i32 %ctl, <2 x i64> %intkey, <2 x i64> %enkey_lo, <2
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: loadiwkey %xmm2, %xmm1
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_loadiwkey:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; EGPR-NEXT: loadiwkey %xmm2, %xmm1 # encoding: [0xf3,0x0f,0x38,0xdc,0xca]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
tail call void @llvm.x86.loadiwkey(<2 x i64> %intkey, <2 x i64> %enkey_lo, <2 x i64> %enkey_hi, i32 %ctl)
ret void
@@ -25,6 +32,17 @@ define i32 @test_encodekey128_u32(i32 %htype, <2 x i64> %key, ptr nocapture %h)
; CHECK-NEXT: movups %xmm5, 64(%rsi)
; CHECK-NEXT: movups %xmm6, 80(%rsi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_encodekey128_u32:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: encodekey128 %edi, %eax # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xfa,0xc7]
+; EGPR-NEXT: movups %xmm0, (%rsi) # encoding: [0x0f,0x11,0x06]
+; EGPR-NEXT: movups %xmm1, 16(%rsi) # encoding: [0x0f,0x11,0x4e,0x10]
+; EGPR-NEXT: movups %xmm2, 32(%rsi) # encoding: [0x0f,0x11,0x56,0x20]
+; EGPR-NEXT: movups %xmm4, 48(%rsi) # encoding: [0x0f,0x11,0x66,0x30]
+; EGPR-NEXT: movups %xmm5, 64(%rsi) # encoding: [0x0f,0x11,0x6e,0x40]
+; EGPR-NEXT: movups %xmm6, 80(%rsi) # encoding: [0x0f,0x11,0x76,0x50]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey128(i32 %htype, <2 x i64> %key)
%1 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 1
@@ -60,6 +78,18 @@ define i32 @test_encodekey256_u32(i32 %htype, <2 x i64> %key_lo, <2 x i64> %key_
; CHECK-NEXT: movups %xmm5, 80(%rsi)
; CHECK-NEXT: movups %xmm6, 96(%rsi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_encodekey256_u32:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: encodekey256 %edi, %eax # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xfb,0xc7]
+; EGPR-NEXT: movups %xmm0, (%rsi) # encoding: [0x0f,0x11,0x06]
+; EGPR-NEXT: movups %xmm1, 16(%rsi) # encoding: [0x0f,0x11,0x4e,0x10]
+; EGPR-NEXT: movups %xmm2, 32(%rsi) # encoding: [0x0f,0x11,0x56,0x20]
+; EGPR-NEXT: movups %xmm3, 48(%rsi) # encoding: [0x0f,0x11,0x5e,0x30]
+; EGPR-NEXT: movups %xmm4, 64(%rsi) # encoding: [0x0f,0x11,0x66,0x40]
+; EGPR-NEXT: movups %xmm5, 80(%rsi) # encoding: [0x0f,0x11,0x6e,0x50]
+; EGPR-NEXT: movups %xmm6, 96(%rsi) # encoding: [0x0f,0x11,0x76,0x60]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey256(i32 %htype, <2 x i64> %key_lo, <2 x i64> %key_hi)
%1 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 1
@@ -94,6 +124,14 @@ define zeroext i8 @test_mm_aesenc256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_mm_aesenc256kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesenc256kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xde,0x06]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesenc256kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -110,6 +148,14 @@ define zeroext i8 @test_mm_aesdec256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_mm_aesdec256kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesdec256kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdf,0x06]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesdec256kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -126,6 +172,14 @@ define zeroext i8 @test_mm_aesenc128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_mm_aesenc128kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesenc128kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdc,0x06]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesenc128kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -142,6 +196,14 @@ define zeroext i8 @test_mm_aesdec128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_mm_aesdec128kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesdec128kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdd,0x06]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesdec128kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -173,6 +235,29 @@ define zeroext i8 @test__mm_aesencwide128kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test__mm_aesencwide128kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
+; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
+; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
+; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
+; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
+; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
+; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
+; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesencwide128kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x02]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
+; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
+; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
+; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
+; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
+; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
+; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
@@ -240,6 +325,29 @@ define zeroext i8 @test__mm_aesdecwide128kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test__mm_aesdecwide128kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
+; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
+; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
+; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
+; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
+; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
+; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
+; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesdecwide128kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x0a]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
+; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
+; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
+; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
+; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
+; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
+; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
@@ -307,6 +415,29 @@ define zeroext i8 @test__mm_aesencwide256kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test__mm_aesencwide256kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
+; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
+; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
+; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
+; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
+; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
+; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
+; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesencwide256kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x12]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
+; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
+; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
+; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
+; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
+; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
+; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
@@ -374,6 +505,29 @@ define zeroext i8 @test__mm_aesdecwide256kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test__mm_aesdecwide256kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
+; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
+; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
+; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
+; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
+; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
+; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
+; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesdecwide256kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x1a]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
+; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
+; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
+; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
+; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
+; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
+; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
diff --git a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
index fa569affdd9ff3..42fe8d4f3f7d84 100644
--- a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
@@ -1,11 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+usermsr | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+usermsr,+egpr | FileCheck %s --check-prefixes=EGPR
define i64 @test_int_x86_urdmsr(i64 %A) nounwind {
; X64-LABEL: test_int_x86_urdmsr:
; X64: # %bb.0:
; X64-NEXT: urdmsr %rdi, %rax # encoding: [0xf2,0x0f,0x38,0xf8,0xc7]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_urdmsr:
+; EGPR: # %bb.0:
+; EGPR-NEXT: urdmsr %rdi, %rax # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf8,0xc7]
+; EGPR-NEXT: retq # encoding: [0xc3]
%ret = call i64 @llvm.x86.urdmsr(i64 %A)
ret i64 %ret
}
@@ -15,6 +21,11 @@ define i64 @test_int_x86_urdmsr_const() nounwind {
; X64: # %bb.0:
; X64-NEXT: urdmsr $123, %rax # encoding: [0xc4,0xe7,0x7b,0xf8,0xc0,0x7b,0x00,0x00,0x00]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_urdmsr_const:
+; EGPR: # %bb.0:
+; EGPR-NEXT: urdmsr $123, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe7,0x7b,0xf8,0xc0,0x7b,0x00,0x00,0x00]
+; EGPR-NEXT: retq # encoding: [0xc3]
%ret = call i64 @llvm.x86.urdmsr(i64 123)
ret i64 %ret
}
@@ -26,6 +37,13 @@ define i64 @test_int_x86_urdmsr_const_i64() nounwind {
; X64-NEXT: # imm = 0x1FFFFFFFF
; X64-NEXT: urdmsr %rax, %rax # encoding: [0xf2,0x0f,0x38,0xf8,0xc0]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_urdmsr_const_i64:
+; EGPR: # %bb.0:
+; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
+; EGPR-NEXT: # imm = 0x1FFFFFFFF
+; EGPR-NEXT: urdmsr %rax, %rax # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf8,0xc0]
+; EGPR-NEXT: retq # encoding: [0xc3]
%ret = call i64 @llvm.x86.urdmsr(i64 8589934591)
ret i64 %ret
}
@@ -37,6 +55,11 @@ define void @test_int_x86_uwrmsr(i64 %A, i64 %B) nounwind {
; X64: # %bb.0:
; X64-NEXT: uwrmsr %rsi, %rdi # encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_uwrmsr:
+; EGPR: # %bb.0:
+; EGPR-NEXT: uwrmsr %rsi, %rdi # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
+; EGPR-NEXT: retq # encoding: [0xc3]
call void @llvm.x86.uwrmsr(i64 %A, i64 %B)
ret void
}
@@ -46,6 +69,11 @@ define void @test_int_x86_uwrmsr_const(i64 %A) nounwind {
; X64: # %bb.0:
; X64-NEXT: uwrmsr %rdi, $123 # encoding: [0xc4,0xe7,0x7a,0xf8,0xc7,0x7b,0x00,0x00,0x00]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_uwrmsr_const:
+; EGPR: # %bb.0:
+; EGPR-NEXT: uwrmsr %rdi, $123 # EVEX TO VEX Compression encoding: [0xc4,0xe7,0x7a,0xf8,0xc7,0x7b,0x00,0x00,0x00]
+; EGPR-NEXT: retq # encoding: [0xc3]
call void @llvm.x86.uwrmsr(i64 123, i64 %A)
ret void
}
@@ -57,6 +85,13 @@ define void @test_int_x86_uwrmsr_const_i64(i64 %A) nounwind {
; X64-NEXT: # imm = 0x1FFFFFFFF
; X64-NEXT: uwrmsr %rdi, %rax # encoding: [0xf3,0x0f,0x38,0xf8,0xc7]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_uwrmsr_const_i64:
+; EGPR: # %bb.0:
+; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
+; EGPR-NEXT: # imm = 0x1FFFFFFFF
+; EGPR-NEXT: uwrmsr %rdi, %rax # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xf8,0xc7]
+; EGPR-NEXT: retq # encoding: [0xc3]
call void @llvm.x86.uwrmsr(i64 8589934591, i64 %A)
ret void
}
diff --git a/llvm/test/MC/Disassembler/X86/apx/enqcmd.txt b/llvm/test/MC/Disassembler/X86/apx/enqcmd.txt
new file mode 100644
index 00000000000000..5b3dec4165dcb7
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/enqcmd.txt
@@ -0,0 +1,38 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+## enqcmd
+
+# ATT: enqcmd 123(%eax,%ebx,4), %ecx
+# INTEL: enqcmd ecx, zmmword ptr [eax + 4*ebx + 123]
+0x67,0x62,0xf4,0x7f,0x08,0xf8,0x4c,0x98,0x7b
+
+# ATT: enqcmd 123(%rax,%rbx,4), %r9
+# INTEL: enqcmd r9, zmmword ptr [rax + 4*rbx + 123]
+0x62,0x74,0x7f,0x08,0xf8,0x4c,0x98,0x7b
+
+# ATT: enqcmd 291(%r28d,%r29d,4), %r18d
+# INTEL: enqcmd r18d, zmmword ptr [r28d + 4*r29d + 291]
+0x67,0x62,0x8c,0x7b,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: enqcmd 291(%r28,%r29,4), %r19
+# INTEL: enqcmd r19, zmmword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x7b,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00
+
+## enqcmds
+
+# ATT: enqcmds 123(%eax,%ebx,4), %ecx
+# INTEL: enqcmds ecx, zmmword ptr [eax + 4*ebx + 123]
+0x67,0x62,0xf4,0x7e,0x08,0xf8,0x4c,0x98,0x7b
+
+# ATT: enqcmds 123(%rax,%rbx,4), %r9
+# INTEL: enqcmds r9, zmmword ptr [rax + 4*rbx + 123]
+0x62,0x74,0x7e,0x08,0xf8,0x4c,0x98,0x7b
+
+# ATT: enqcmds 291(%r28d,%r29d,4), %r18d
+# INTEL: enqcmds r18d, zmmword ptr [r28d + 4*r29d + 291]
+0x67,0x62,0x8c,0x7a,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: enqcmds 291(%r28,%r29,4), %r19
+# INTEL: enqcmds r19, zmmword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x7a,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/keylocker.txt b/llvm/test/MC/Disassembler/X86/apx/keylocker.txt
new file mode 100644
index 00000000000000..c1ddef9ed4233d
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/keylocker.txt
@@ -0,0 +1,102 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+## aesdec128kl
+
+# ATT: aesdec128kl 123(%rax,%rbx,4), %xmm12
+# INTEL: aesdec128kl xmm12, [rax + 4*rbx + 123]
+0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b
+
+# ATT: aesdec128kl 291(%r28,%r29,4), %xmm12
+# INTEL: aesdec128kl xmm12, [r28 + 4*r29 + 291]
+0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00
+
+## aesdec256kl
+
+# ATT: aesdec256kl 123(%rax,%rbx,4), %xmm12
+# INTEL: aesdec256kl xmm12, [rax + 4*rbx + 123]
+0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b
+
+# ATT: aesdec256kl 291(%r28,%r29,4), %xmm12
+# INTEL: aesdec256kl xmm12, [r28 + 4*r29 + 291]
+0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00
+
+## aesdecwide128kl
+
+# ATT: aesdecwide128kl 123(%rax,%rbx,4)
+# INTEL: aesdecwide128kl [rax + 4*rbx + 123]
+0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b
+
+# ATT: aesdecwide128kl 291(%r28,%r29,4)
+# INTEL: aesdecwide128kl [r28 + 4*r29 + 291]
+0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00
+
+## aesdecwide256kl
+
+# ATT: aesdecwide256kl 123(%rax,%rbx,4)
+# INTEL: aesdecwide256kl [rax + 4*rbx + 123]
+0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b
+
+# ATT: aesdecwide256kl 291(%r28,%r29,4)
+# INTEL: aesdecwide256kl [r28 + 4*r29 + 291]
+0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00
+
+## aesenc128kl
+
+# ATT: aesenc128kl 123(%rax,%rbx,4), %xmm12
+# INTEL: aesenc128kl xmm12, [rax + 4*rbx + 123]
+0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b
+
+# ATT: aesenc128kl 291(%r28,%r29,4), %xmm12
+# INTEL: aesenc128kl xmm12, [r28 + 4*r29 + 291]
+0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00
+
+## aesenc256kl
+
+# ATT: aesenc256kl 123(%rax,%rbx,4), %xmm12
+# INTEL: aesenc256kl xmm12, [rax + 4*rbx + 123]
+0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b
+
+# ATT: aesenc256kl 291(%r28,%r29,4), %xmm12
+# INTEL: aesenc256kl xmm12, [r28 + 4*r29 + 291]
+0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00
+
+## aesencwide128kl
+
+# ATT: aesencwide128kl 123(%rax,%rbx,4)
+# INTEL: aesencwide128kl [rax + 4*rbx + 123]
+0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b
+
+# ATT: aesencwide128kl 291(%r28,%r29,4)
+# INTEL: aesencwide128kl [r28 + 4*r29 + 291]
+0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00
+
+## aesencwide256kl
+
+# ATT: aesencwide256kl 123(%rax,%rbx,4)
+# INTEL: aesencwide256kl [rax + 4*rbx + 123]
+0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b
+
+# ATT: aesencwide256kl 291(%r28,%r29,4)
+# INTEL: aesencwide256kl [r28 + 4*r29 + 291]
+0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00
+
+## encodekey128
+
+# ATT: encodekey128 %ecx, %edx
+# INTEL: encodekey128 edx, ecx
+0x62,0xf4,0x7e,0x08,0xda,0xd1
+
+# ATT: encodekey128 %r18d, %r22d
+# INTEL: encodekey128 r22d, r18d
+0x62,0xec,0x7e,0x08,0xda,0xf2
+
+## encodekey256
+
+# ATT: encodekey256 %ecx, %edx
+# INTEL: encodekey256 edx, ecx
+0x62,0xf4,0x7e,0x08,0xdb,0xd1
+
+# ATT: encodekey256 %r18d, %r22d
+# INTEL: encodekey256 r22d, r18d
+0x62,0xec,0x7e,0x08,0xdb,0xf2
diff --git a/llvm/test/MC/Disassembler/X86/apx/user-msr.txt b/llvm/test/MC/Disassembler/X86/apx/user-msr.txt
new file mode 100644
index 00000000000000..60cdab132485c6
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/user-msr.txt
@@ -0,0 +1,38 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+## urdmsr
+
+# ATT: urdmsr $123, %r9
+# INTEL: urdmsr r9, 123
+0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT: urdmsr %r9, %r15
+# INTEL: urdmsr r15, r9
+0x62,0x54,0x7f,0x08,0xf8,0xf9
+
+# ATT: urdmsr $123, %r19
+# INTEL: urdmsr r19, 123
+0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00
+
+# ATT: urdmsr %r19, %r23
+# INTEL: urdmsr r23, r19
+0x62,0xec,0x7f,0x08,0xf8,0xfb
+
+## uwrmsr
+
+# ATT: uwrmsr %r9, $123
+# INTEL: uwrmsr 123, r9
+0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT: uwrmsr %r9, %r15
+# INTEL: uwrmsr r15, r9
+0x62,0x54,0x7e,0x08,0xf8,0xf9
+
+# ATT: uwrmsr %r19, $123
+# INTEL: uwrmsr 123, r19
+0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00
+
+# ATT: uwrmsr %r19, %r23
+# INTEL: uwrmsr r23, r19
+0x62,0xec,0x7e,0x08,0xf8,0xfb
diff --git a/llvm/test/MC/X86/apx/enqcmd-att.s b/llvm/test/MC/X86/apx/enqcmd-att.s
new file mode 100644
index 00000000000000..36975c512d10b1
--- /dev/null
+++ b/llvm/test/MC/X86/apx/enqcmd-att.s
@@ -0,0 +1,41 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-8: error:
+# ERROR-NOT: error:
+
+## enqcmd
+
+# CHECK: {evex} enqcmd 123(%eax,%ebx,4), %ecx
+# CHECK: encoding: [0x67,0x62,0xf4,0x7f,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmd 123(%eax,%ebx,4), %ecx
+
+# CHECK: {evex} enqcmd 123(%rax,%rbx,4), %r9
+# CHECK: encoding: [0x62,0x74,0x7f,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmd 123(%rax,%rbx,4), %r9
+
+# CHECK: enqcmd 291(%r28d,%r29d,4), %r18d
+# CHECK: encoding: [0x67,0x62,0x8c,0x7b,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
+ enqcmd 291(%r28d,%r29d,4), %r18d
+
+# CHECK: enqcmd 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0x7b,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ enqcmd 291(%r28,%r29,4), %r19
+
+## enqcmds
+
+# CHECK: {evex} enqcmds 123(%eax,%ebx,4), %ecx
+# CHECK: encoding: [0x67,0x62,0xf4,0x7e,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmds 123(%eax,%ebx,4), %ecx
+
+# CHECK: {evex} enqcmds 123(%rax,%rbx,4), %r9
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmds 123(%rax,%rbx,4), %r9
+
+# CHECK: enqcmds 291(%r28d,%r29d,4), %r18d
+# CHECK: encoding: [0x67,0x62,0x8c,0x7a,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
+ enqcmds 291(%r28d,%r29d,4), %r18d
+
+# CHECK: enqcmds 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0x7a,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ enqcmds 291(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/enqcmd-intel.s b/llvm/test/MC/X86/apx/enqcmd-intel.s
new file mode 100644
index 00000000000000..8f4a48e9e6f6a1
--- /dev/null
+++ b/llvm/test/MC/X86/apx/enqcmd-intel.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+## enqcmd
+
+# CHECK: {evex} enqcmd ecx, zmmword ptr [eax + 4*ebx + 123]
+# CHECK: encoding: [0x67,0x62,0xf4,0x7f,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmd ecx, zmmword ptr [eax + 4*ebx + 123]
+
+# CHECK: {evex} enqcmd r9, zmmword ptr [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7f,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmd r9, zmmword ptr [rax + 4*rbx + 123]
+
+# CHECK: enqcmd r18d, zmmword ptr [r28d + 4*r29d + 291]
+# CHECK: encoding: [0x67,0x62,0x8c,0x7b,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
+ enqcmd r18d, zmmword ptr [r28d + 4*r29d + 291]
+
+# CHECK: enqcmd r19, zmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x7b,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ enqcmd r19, zmmword ptr [r28 + 4*r29 + 291]
+
+## enqcmds
+
+# CHECK: {evex} enqcmds ecx, zmmword ptr [eax + 4*ebx + 123]
+# CHECK: encoding: [0x67,0x62,0xf4,0x7e,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmds ecx, zmmword ptr [eax + 4*ebx + 123]
+
+# CHECK: {evex} enqcmds r9, zmmword ptr [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmds r9, zmmword ptr [rax + 4*rbx + 123]
+
+# CHECK: enqcmds r18d, zmmword ptr [r28d + 4*r29d + 291]
+# CHECK: encoding: [0x67,0x62,0x8c,0x7a,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
+ enqcmds r18d, zmmword ptr [r28d + 4*r29d + 291]
+
+# CHECK: enqcmds r19, zmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x7a,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ enqcmds r19, zmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/keylocker-att.s b/llvm/test/MC/X86/apx/keylocker-att.s
new file mode 100644
index 00000000000000..7c8db319df74a7
--- /dev/null
+++ b/llvm/test/MC/X86/apx/keylocker-att.s
@@ -0,0 +1,105 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-20: error:
+# ERROR-NOT: error:
+
+## aesdec128kl
+
+# CHECK: {evex} aesdec128kl 123(%rax,%rbx,4), %xmm12
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b]
+ {evex} aesdec128kl 123(%rax,%rbx,4), %xmm12
+
+# CHECK: aesdec128kl 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesdec128kl 291(%r28,%r29,4), %xmm12
+
+## aesdec256kl
+
+# CHECK: {evex} aesdec256kl 123(%rax,%rbx,4), %xmm12
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b]
+ {evex} aesdec256kl 123(%rax,%rbx,4), %xmm12
+
+# CHECK: aesdec256kl 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesdec256kl 291(%r28,%r29,4), %xmm12
+
+## aesdecwide128kl
+
+# CHECK: {evex} aesdecwide128kl 123(%rax,%rbx,4)
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b]
+ {evex} aesdecwide128kl 123(%rax,%rbx,4)
+
+# CHECK: aesdecwide128kl 291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00]
+ aesdecwide128kl 291(%r28,%r29,4)
+
+## aesdecwide256kl
+
+# CHECK: {evex} aesdecwide256kl 123(%rax,%rbx,4)
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b]
+ {evex} aesdecwide256kl 123(%rax,%rbx,4)
+
+# CHECK: aesdecwide256kl 291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ aesdecwide256kl 291(%r28,%r29,4)
+
+## aesenc128kl
+
+# CHECK: {evex} aesenc128kl 123(%rax,%rbx,4), %xmm12
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b]
+ {evex} aesenc128kl 123(%rax,%rbx,4), %xmm12
+
+# CHECK: aesenc128kl 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesenc128kl 291(%r28,%r29,4), %xmm12
+
+## aesenc256kl
+
+# CHECK: {evex} aesenc256kl 123(%rax,%rbx,4), %xmm12
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b]
+ {evex} aesenc256kl 123(%rax,%rbx,4), %xmm12
+
+# CHECK: aesenc256kl 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesenc256kl 291(%r28,%r29,4), %xmm12
+
+## aesencwide128kl
+
+# CHECK: {evex} aesencwide128kl 123(%rax,%rbx,4)
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b]
+ {evex} aesencwide128kl 123(%rax,%rbx,4)
+
+# CHECK: aesencwide128kl 291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00]
+ aesencwide128kl 291(%r28,%r29,4)
+
+## aesencwide256kl
+
+# CHECK: {evex} aesencwide256kl 123(%rax,%rbx,4)
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b]
+ {evex} aesencwide256kl 123(%rax,%rbx,4)
+
+# CHECK: aesencwide256kl 291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00]
+ aesencwide256kl 291(%r28,%r29,4)
+
+## encodekey128
+
+# CHECK: {evex} encodekey128 %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xda,0xd1]
+ {evex} encodekey128 %ecx, %edx
+
+# CHECK: encodekey128 %r18d, %r22d
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xda,0xf2]
+ encodekey128 %r18d, %r22d
+
+## encodekey256
+
+# CHECK: {evex} encodekey256 %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xdb,0xd1]
+ {evex} encodekey256 %ecx, %edx
+
+# CHECK: encodekey256 %r18d, %r22d
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xdb,0xf2]
+ encodekey256 %r18d, %r22d
diff --git a/llvm/test/MC/X86/apx/keylocker-intel.s b/llvm/test/MC/X86/apx/keylocker-intel.s
new file mode 100644
index 00000000000000..b59fa001483d68
--- /dev/null
+++ b/llvm/test/MC/X86/apx/keylocker-intel.s
@@ -0,0 +1,101 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+## aesdec128kl
+
+# CHECK: {evex} aesdec128kl xmm12, [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b]
+ {evex} aesdec128kl xmm12, [rax + 4*rbx + 123]
+
+# CHECK: aesdec128kl xmm12, [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesdec128kl xmm12, [r28 + 4*r29 + 291]
+
+## aesdec256kl
+
+# CHECK: {evex} aesdec256kl xmm12, [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b]
+ {evex} aesdec256kl xmm12, [rax + 4*rbx + 123]
+
+# CHECK: aesdec256kl xmm12, [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesdec256kl xmm12, [r28 + 4*r29 + 291]
+
+## aesdecwide128kl
+
+# CHECK: {evex} aesdecwide128kl [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b]
+ {evex} aesdecwide128kl [rax + 4*rbx + 123]
+
+# CHECK: aesdecwide128kl [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00]
+ aesdecwide128kl [r28 + 4*r29 + 291]
+
+## aesdecwide256kl
+
+# CHECK: {evex} aesdecwide256kl [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b]
+ {evex} aesdecwide256kl [rax + 4*rbx + 123]
+
+# CHECK: aesdecwide256kl [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ aesdecwide256kl [r28 + 4*r29 + 291]
+
+## aesenc128kl
+
+# CHECK: {evex} aesenc128kl xmm12, [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b]
+ {evex} aesenc128kl xmm12, [rax + 4*rbx + 123]
+
+# CHECK: aesenc128kl xmm12, [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesenc128kl xmm12, [r28 + 4*r29 + 291]
+
+## aesenc256kl
+
+# CHECK: {evex} aesenc256kl xmm12, [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b]
+ {evex} aesenc256kl xmm12, [rax + 4*rbx + 123]
+
+# CHECK: aesenc256kl xmm12, [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesenc256kl xmm12, [r28 + 4*r29 + 291]
+
+## aesencwide128kl
+
+# CHECK: {evex} aesencwide128kl [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b]
+ {evex} aesencwide128kl [rax + 4*rbx + 123]
+
+# CHECK: aesencwide128kl [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00]
+ aesencwide128kl [r28 + 4*r29 + 291]
+
+## aesencwide256kl
+
+# CHECK: {evex} aesencwide256kl [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b]
+ {evex} aesencwide256kl [rax + 4*rbx + 123]
+
+# CHECK: aesencwide256kl [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00]
+ aesencwide256kl [r28 + 4*r29 + 291]
+
+## encodekey128
+
+# CHECK: {evex} encodekey128 edx, ecx
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xda,0xd1]
+ {evex} encodekey128 edx, ecx
+
+# CHECK: encodekey128 r22d, r18d
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xda,0xf2]
+ encodekey128 r22d, r18d
+
+## encodekey256
+
+# CHECK: {evex} encodekey256 edx, ecx
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xdb,0xd1]
+ {evex} encodekey256 edx, ecx
+
+# CHECK: encodekey256 r22d, r18d
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xdb,0xf2]
+ encodekey256 r22d, r18d
diff --git a/llvm/test/MC/X86/apx/user-msr-att.s b/llvm/test/MC/X86/apx/user-msr-att.s
new file mode 100644
index 00000000000000..59df5895d53ec1
--- /dev/null
+++ b/llvm/test/MC/X86/apx/user-msr-att.s
@@ -0,0 +1,41 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-8: error:
+# ERROR-NOT: error:
+
+## urdmsr
+
+# CHECK: {evex} urdmsr $123, %r9
+# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} urdmsr $123, %r9
+
+# CHECK: {evex} urdmsr %r9, %r15
+# CHECK: encoding: [0x62,0x54,0x7f,0x08,0xf8,0xf9]
+ {evex} urdmsr %r9, %r15
+
+# CHECK: urdmsr $123, %r19
+# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ urdmsr $123, %r19
+
+# CHECK: urdmsr %r19, %r23
+# CHECK: encoding: [0x62,0xec,0x7f,0x08,0xf8,0xfb]
+ urdmsr %r19, %r23
+
+## uwrmsr
+
+# CHECK: {evex} uwrmsr %r9, $123
+# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} uwrmsr %r9, $123
+
+# CHECK: {evex} uwrmsr %r9, %r15
+# CHECK: encoding: [0x62,0x54,0x7e,0x08,0xf8,0xf9]
+ {evex} uwrmsr %r9, %r15
+
+# CHECK: uwrmsr %r19, $123
+# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ uwrmsr %r19, $123
+
+# CHECK: uwrmsr %r19, %r23
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xf8,0xfb]
+ uwrmsr %r19, %r23
diff --git a/llvm/test/MC/X86/apx/user-msr-intel.s b/llvm/test/MC/X86/apx/user-msr-intel.s
new file mode 100644
index 00000000000000..b6f43e85834c08
--- /dev/null
+++ b/llvm/test/MC/X86/apx/user-msr-intel.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+## urdmsr
+
+# CHECK: {evex} urdmsr r9, 123
+# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} urdmsr r9, 123
+
+# CHECK: {evex} urdmsr r15, r9
+# CHECK: encoding: [0x62,0x54,0x7f,0x08,0xf8,0xf9]
+ {evex} urdmsr r15, r9
+
+# CHECK: urdmsr r19, 123
+# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ urdmsr r19, 123
+
+# CHECK: urdmsr r23, r19
+# CHECK: encoding: [0x62,0xec,0x7f,0x08,0xf8,0xfb]
+ urdmsr r23, r19
+
+## uwrmsr
+
+# CHECK: {evex} uwrmsr 123, r9
+# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} uwrmsr 123, r9
+
+# CHECK: {evex} uwrmsr r15, r9
+# CHECK: encoding: [0x62,0x54,0x7e,0x08,0xf8,0xf9]
+ {evex} uwrmsr r15, r9
+
+# CHECK: uwrmsr 123, r19
+# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ uwrmsr 123, r19
+
+# CHECK: uwrmsr r23, r19
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xf8,0xfb]
+ uwrmsr r23, r19
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 9ee1472bdf5cc1..23886a3468243e 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -214,6 +214,8 @@ static inline bool inheritsFrom(InstructionContext child,
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE)) ||
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE));
case IC_EVEX_OPSIZE_ADSIZE:
+ case IC_EVEX_XS_ADSIZE:
+ case IC_EVEX_XD_ADSIZE:
return false;
case IC_EVEX_K:
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_K)) ||
@@ -894,8 +896,12 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
for (unsigned index = 0; index < ATTR_max; ++index) {
o.indent(i * 2);
- if ((index & ATTR_EVEX) && (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
+ if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_OPSIZE))
o << "IC_EVEX_OPSIZE_ADSIZE";
+ else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XD))
+ o << "IC_EVEX_XD_ADSIZE";
+ else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XS))
+ o << "IC_EVEX_XS_ADSIZE";
else if (index & ATTR_EVEXNF) {
o << "IC_EVEX";
if (index & ATTR_REXW)
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index fb430676c504b9..18f961065c2332 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -188,6 +188,7 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
#define EVEX_NF(n) (HasEVEX_NF ? n##_NF : n)
#define EVEX_B_NF(n) (HasEVEX_B ? EVEX_NF(n##_B) : EVEX_NF(n))
+#define EVEX_KB_ADSIZE(n) AdSize == X86Local::AdSize32 ? n##_ADSIZE : EVEX_KB(n)
InstructionContext RecognizableInstr::insnContext() const {
InstructionContext insnContext;
@@ -277,14 +278,11 @@ InstructionContext RecognizableInstr::insnContext() const {
}
// No L, no W
else if (OpPrefix == X86Local::PD) {
- if (AdSize == X86Local::AdSize32)
- insnContext = IC_EVEX_OPSIZE_ADSIZE;
- else
- insnContext = EVEX_KB(IC_EVEX_OPSIZE);
+ insnContext = EVEX_KB_ADSIZE(IC_EVEX_OPSIZE);
} else if (OpPrefix == X86Local::XD)
- insnContext = EVEX_KB(IC_EVEX_XD);
+ insnContext = EVEX_KB_ADSIZE(IC_EVEX_XD);
else if (OpPrefix == X86Local::XS)
- insnContext = EVEX_KB(IC_EVEX_XS);
+ insnContext = EVEX_KB_ADSIZE(IC_EVEX_XS);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB(IC_EVEX);
else {
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