[llvm] [RISCV] Macro-fusion support for veyron-v1 CPU. (PR #70012)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 25 21:20:23 PST 2024
================
@@ -18,6 +18,101 @@
using namespace llvm;
+static bool checkRegisters(Register FirstDest, const MachineInstr &SecondMI) {
+ if (!SecondMI.getOperand(1).isReg())
+ return false;
+
+ if (SecondMI.getOperand(1).getReg() != FirstDest)
+ return false;
+
+ // If the input is virtual make sure this is the only user.
+ if (FirstDest.isVirtual()) {
+ auto &MRI = SecondMI.getMF()->getRegInfo();
+ return MRI.hasOneNonDBGUse(FirstDest);
+ }
+
+ return SecondMI.getOperand(0).getReg() == FirstDest;
+}
+
+// Fuse load with add:
+// add rd, rs1, rs2
+// ld rd, 0(rd)
+static bool isLDADD(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
+ if (SecondMI.getOpcode() != RISCV::LD)
----------------
topperc wrote:
@mgudim Is this fusion reall restricted to just 64-bit load?
https://github.com/llvm/llvm-project/pull/70012
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