[llvm] [DAG] Add a one-use check to concat -> scalar_to_vector fold. (PR #79510)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: David Green (davemgreen)

<details>
<summary>Changes</summary>

Without this we can end up with multiple copies from gpr->fpr.

---
Full diff: https://github.com/llvm/llvm-project/pull/79510.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+1-1) 
- (modified) llvm/test/CodeGen/AArch64/pr79100.ll (+10-20) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2947ca7532b80d..87184fe409eade 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -23842,7 +23842,7 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
     }
 
     // concat_vectors(scalar, undef) -> scalar_to_vector(scalar)
-    if (!Scalar.getValueType().isVector()) {
+    if (!Scalar.getValueType().isVector() && In.hasOneUse()) {
       // If the bitcast type isn't legal, it might be a trunc of a legal type;
       // look through the trunc so we can still do the transform:
       //   concat_vectors(trunc(scalar), undef) -> scalar_to_vector(scalar)
diff --git a/llvm/test/CodeGen/AArch64/pr79100.ll b/llvm/test/CodeGen/AArch64/pr79100.ll
index 8e8cd7ed53b63e..a6e002a5c3d7f3 100644
--- a/llvm/test/CodeGen/AArch64/pr79100.ll
+++ b/llvm/test/CodeGen/AArch64/pr79100.ll
@@ -1,26 +1,16 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s -mtriple=aarch64 -global-isel 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -mtriple=aarch64 -global-isel 2>&1 | FileCheck %s --check-prefixes=CHECK
 
 define <16 x i8> @test_2(i64 %0) {
-; CHECK-SD-LABEL: test_2:
-; CHECK-SD:       // %bb.0: // %Entry
-; CHECK-SD-NEXT:    fmov d1, x0
-; CHECK-SD-NEXT:    fmov d2, x0
-; CHECK-SD-NEXT:    movi v0.16b, #15
-; CHECK-SD-NEXT:    ushr v1.8b, v1.8b, #4
-; CHECK-SD-NEXT:    zip1 v1.16b, v2.16b, v1.16b
-; CHECK-SD-NEXT:    and v0.16b, v1.16b, v0.16b
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: test_2:
-; CHECK-GI:       // %bb.0: // %Entry
-; CHECK-GI-NEXT:    fmov d1, x0
-; CHECK-GI-NEXT:    movi v0.16b, #15
-; CHECK-GI-NEXT:    ushr v2.8b, v1.8b, #4
-; CHECK-GI-NEXT:    zip1 v1.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT:    and v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: test_2:
+; CHECK:       // %bb.0: // %Entry
+; CHECK-NEXT:    fmov d1, x0
+; CHECK-NEXT:    movi v0.16b, #15
+; CHECK-NEXT:    ushr v2.8b, v1.8b, #4
+; CHECK-NEXT:    zip1 v1.16b, v1.16b, v2.16b
+; CHECK-NEXT:    and v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    ret
 Entry:
   %1 = bitcast i64 %0 to <8 x i8>
   %2 = lshr <8 x i8> %1, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>

``````````

</details>


https://github.com/llvm/llvm-project/pull/79510