[llvm] [RISCV] Add TuneNoSinkSplatOperands to sifive-p670 (PR #79492)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Michael Maitland (michaelmaitland)

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<summary>Changes</summary>



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Full diff: https://github.com/llvm/llvm-project/pull/79492.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+2-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 03ca505d100df4f..59bb811058d4886 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -280,7 +280,8 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
                                       [TuneNoDefaultUnroll,
                                        TuneConditionalCompressedMoveFusion,
                                        TuneLUIADDIFusion,
-                                       TuneAUIPCADDIFusion]>;
+                                       TuneAUIPCADDIFusion,
+                                       TuneNoSinkSplatOperands]>;
 
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
                                               SyntacoreSCR1Model,

``````````

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https://github.com/llvm/llvm-project/pull/79492