[llvm] 71c52e4 - [gn build] Port 3fdb431b6369

[Nico Weber via llvm-commits]

Author: Nico Weber
Date: 2024-01-25T08:41:44-05:00
New Revision: 71c52e4236a9eb586a9271240442c5dbfce17488

URL: https://github.com/llvm/llvm-project/commit/71c52e4236a9eb586a9271240442c5dbfce17488
DIFF: https://github.com/llvm/llvm-project/commit/71c52e4236a9eb586a9271240442c5dbfce17488.diff

LOG: [gn build] Port 3fdb431b6369

Added: 
    

Modified: 
    llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn

Removed: 
    


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diff  --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
index 45239649569b46d..01bb5e54bd5dbae 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
@@ -14,6 +14,12 @@ tablegen("RISCVGenCompressInstEmitter") {
   td_file = "RISCV.td"
 }
 
+tablegen("RISCVGenMacroFusion") {
+  visibility = [ ":LLVMRISCVCodeGen" ]
+  args = [ "-gen-macro-fusion-pred" ]
+  td_file = "RISCV.td"
+}
+
 tablegen("RISCVGenDAGISel") {
   visibility = [ ":LLVMRISCVCodeGen" ]
   args = [ "-gen-dag-isel" ]
@@ -71,6 +77,7 @@ static_library("LLVMRISCVCodeGen") {
     ":RISCVGenDAGISel",
     ":RISCVGenGlobalISel",
     ":RISCVGenMCPseudoLowering",
+    ":RISCVGenMacroFusion",
     ":RISCVGenO0PreLegalizeGICombiner",
     ":RISCVGenPostLegalizeGICombiner",
     ":RISCVGenPreLegalizeGICombiner",
@@ -116,7 +123,6 @@ static_library("LLVMRISCVCodeGen") {
     "RISCVInsertWriteVXRM.cpp",
     "RISCVInstrInfo.cpp",
     "RISCVMachineFunctionInfo.cpp",
-    "RISCVMacroFusion.cpp",
     "RISCVMakeCompressible.cpp",
     "RISCVMergeBaseOffset.cpp",
     "RISCVMoveMerger.cpp",