[llvm] 3fdb431 - [RISCV] Use TableGen-based macro fusion (#72224)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 25 01:10:53 PST 2024
Author: Wang Pengcheng
Date: 2024-01-25T17:10:49+08:00
New Revision: 3fdb431b636975f2062b1931158aa4dfce6a3ff1
URL: https://github.com/llvm/llvm-project/commit/3fdb431b636975f2062b1931158aa4dfce6a3ff1
DIFF: https://github.com/llvm/llvm-project/commit/3fdb431b636975f2062b1931158aa4dfce6a3ff1.diff
LOG: [RISCV] Use TableGen-based macro fusion (#72224)
We convert existed macro fusions to TableGen.
Bacause `Fusion` depend on `Instruction` definitions which is defined
below `RISCVFeatures.td`, so we recommend user to add fusion features
when defining new processor.
Added:
llvm/lib/Target/RISCV/RISCVMacroFusion.td
Modified:
llvm/lib/Target/RISCV/CMakeLists.txt
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Removed:
llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
llvm/lib/Target/RISCV/RISCVMacroFusion.h
################################################################################
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index a0c3345ec1bbd7e..ac88cd49db4e4ba 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -5,6 +5,7 @@ set(LLVM_TARGET_DEFINITIONS RISCV.td)
tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
+tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
@@ -43,7 +44,6 @@ add_llvm_target(RISCVCodeGen
RISCVISelDAGToDAG.cpp
RISCVISelLowering.cpp
RISCVMachineFunctionInfo.cpp
- RISCVMacroFusion.cpp
RISCVMergeBaseOffset.cpp
RISCVOptWInstrs.cpp
RISCVPostRAExpandPseudoInsts.cpp
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index e6e879282241dde..27d52c16a4f39d9 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -30,6 +30,12 @@ include "RISCVCallingConv.td"
include "RISCVInstrInfo.td"
include "GISel/RISCVRegisterBanks.td"
+//===----------------------------------------------------------------------===//
+// RISC-V macro fusions.
+//===----------------------------------------------------------------------===//
+
+include "RISCVMacroFusion.td"
+
//===----------------------------------------------------------------------===//
// RISC-V Scheduling Models
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 680b66872286bd9..045173bd63437a2 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1062,30 +1062,6 @@ def TuneDLenFactor2
: SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true",
"Vector unit DLEN(data path width) is half of VLEN">;
-def TuneLUIADDIFusion
- : SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
- "true", "Enable LUI+ADDI macrofusion">;
-
-def TuneAUIPCADDIFusion
- : SubtargetFeature<"auipc-addi-fusion", "HasAUIPCADDIFusion",
- "true", "Enable AUIPC+ADDI macrofusion">;
-
-def TuneZExtHFusion
- : SubtargetFeature<"zexth-fusion", "HasZExtHFusion",
- "true", "Enable SLLI+SRLI to be fused to zero extension of halfword">;
-
-def TuneZExtWFusion
- : SubtargetFeature<"zextw-fusion", "HasZExtWFusion",
- "true", "Enable SLLI+SRLI to be fused to zero extension of word">;
-
-def TuneShiftedZExtWFusion
- : SubtargetFeature<"shifted-zextw-fusion", "HasShiftedZExtWFusion",
- "true", "Enable SLLI+SRLI to be fused when computing (shifted) zero extension of word">;
-
-def TuneLDADDFusion
- : SubtargetFeature<"ld-add-fusion", "HasLDADDFusion",
- "true", "Enable LD+ADD macrofusion.">;
-
def TuneNoDefaultUnroll
: SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
"Disable default unroll preference.">;
diff --git a/llvm/lib/Target/RISCV/RISCVMacroFusion.cpp b/llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
deleted file mode 100644
index f948f05b22f772e..000000000000000
--- a/llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
+++ /dev/null
@@ -1,210 +0,0 @@
-//===- RISCVMacroFusion.cpp - RISC-V Macro Fusion -------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-/// \file This file contains the RISC-V implementation of the DAG scheduling
-/// mutation to pair instructions back to back.
-//
-//===----------------------------------------------------------------------===//
-//
-#include "RISCVMacroFusion.h"
-#include "RISCVSubtarget.h"
-#include "llvm/CodeGen/MacroFusion.h"
-#include "llvm/CodeGen/TargetInstrInfo.h"
-
-using namespace llvm;
-
-static bool checkRegisters(Register FirstDest, const MachineInstr &SecondMI) {
- if (!SecondMI.getOperand(1).isReg())
- return false;
-
- if (SecondMI.getOperand(1).getReg() != FirstDest)
- return false;
-
- // If the input is virtual make sure this is the only user.
- if (FirstDest.isVirtual()) {
- auto &MRI = SecondMI.getMF()->getRegInfo();
- return MRI.hasOneNonDBGUse(FirstDest);
- }
-
- return SecondMI.getOperand(0).getReg() == FirstDest;
-}
-
-// Fuse load with add:
-// add rd, rs1, rs2
-// ld rd, 0(rd)
-static bool isLDADD(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
- if (SecondMI.getOpcode() != RISCV::LD)
- return false;
-
- if (!SecondMI.getOperand(2).isImm())
- return false;
-
- if (SecondMI.getOperand(2).getImm() != 0)
- return false;
-
- // Given SecondMI, when FirstMI is unspecified, we must return
- // if SecondMI may be part of a fused pair at all.
- if (!FirstMI)
- return true;
-
- if (FirstMI->getOpcode() != RISCV::ADD)
- return true;
-
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
-}
-
-// Fuse zero extension of halfword:
-// slli rd, rs1, 48
-// srli rd, rd, 48
-static bool isZExtH(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
- if (SecondMI.getOpcode() != RISCV::SRLI)
- return false;
-
- if (!SecondMI.getOperand(2).isImm())
- return false;
-
- if (SecondMI.getOperand(2).getImm() != 48)
- return false;
-
- // Given SecondMI, when FirstMI is unspecified, we must return
- // if SecondMI may be part of a fused pair at all.
- if (!FirstMI)
- return true;
-
- if (FirstMI->getOpcode() != RISCV::SLLI)
- return false;
-
- if (FirstMI->getOperand(2).getImm() != 48)
- return false;
-
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
-}
-
-// Fuse zero extension of word:
-// slli rd, rs1, 32
-// srli rd, rd, 32
-static bool isZExtW(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
- if (SecondMI.getOpcode() != RISCV::SRLI)
- return false;
-
- if (!SecondMI.getOperand(2).isImm())
- return false;
-
- if (SecondMI.getOperand(2).getImm() != 32)
- return false;
-
- // Given SecondMI, when FirstMI is unspecified, we must return
- // if SecondMI may be part of a fused pair at all.
- if (!FirstMI)
- return true;
-
- if (FirstMI->getOpcode() != RISCV::SLLI)
- return false;
-
- if (FirstMI->getOperand(2).getImm() != 32)
- return false;
-
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
-}
-
-// Fuse shifted zero extension of word:
-// slli rd, rs1, 32
-// srli rd, rd, x
-// where 0 <= x < 32
-static bool isShiftedZExtW(const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
- if (SecondMI.getOpcode() != RISCV::SRLI)
- return false;
-
- if (!SecondMI.getOperand(2).isImm())
- return false;
-
- unsigned SRLIImm = SecondMI.getOperand(2).getImm();
- if (SRLIImm >= 32)
- return false;
-
- // Given SecondMI, when FirstMI is unspecified, we must return
- // if SecondMI may be part of a fused pair at all.
- if (!FirstMI)
- return true;
-
- if (FirstMI->getOpcode() != RISCV::SLLI)
- return false;
-
- if (FirstMI->getOperand(2).getImm() != 32)
- return false;
-
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
-}
-
-// Fuse AUIPC followed by ADDI
-// auipc rd, imm20
-// addi rd, rd, imm12
-static bool isAUIPCADDI(const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
- if (SecondMI.getOpcode() != RISCV::ADDI)
- return false;
- // Assume the 1st instr to be a wildcard if it is unspecified.
- if (!FirstMI)
- return true;
-
- if (FirstMI->getOpcode() != RISCV::AUIPC)
- return false;
-
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
-}
-
-// Fuse LUI followed by ADDI or ADDIW.
-// rd = imm[31:0] which decomposes to
-// lui rd, imm[31:12]
-// addi(w) rd, rd, imm[11:0]
-static bool isLUIADDI(const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
- if (SecondMI.getOpcode() != RISCV::ADDI &&
- SecondMI.getOpcode() != RISCV::ADDIW)
- return false;
- // Assume the 1st instr to be a wildcard if it is unspecified.
- if (!FirstMI)
- return true;
-
- if (FirstMI->getOpcode() != RISCV::LUI)
- return false;
-
- return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
-}
-
-static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
- const TargetSubtargetInfo &TSI,
- const MachineInstr *FirstMI,
- const MachineInstr &SecondMI) {
- const RISCVSubtarget &ST = static_cast<const RISCVSubtarget &>(TSI);
-
- if (ST.hasLUIADDIFusion() && isLUIADDI(FirstMI, SecondMI))
- return true;
-
- if (ST.hasAUIPCADDIFusion() && isAUIPCADDI(FirstMI, SecondMI))
- return true;
-
- if (ST.hasZExtHFusion() && isZExtH(FirstMI, SecondMI))
- return true;
-
- if (ST.hasZExtWFusion() && isZExtW(FirstMI, SecondMI))
- return true;
-
- if (ST.hasShiftedZExtWFusion() && isShiftedZExtW(FirstMI, SecondMI))
- return true;
-
- if (ST.hasLDADDFusion() && isLDADD(FirstMI, SecondMI))
- return true;
-
- return false;
-}
-
-std::unique_ptr<ScheduleDAGMutation> llvm::createRISCVMacroFusionDAGMutation() {
- return createMacroFusionDAGMutation(shouldScheduleAdjacent);
-}
diff --git a/llvm/lib/Target/RISCV/RISCVMacroFusion.h b/llvm/lib/Target/RISCV/RISCVMacroFusion.h
deleted file mode 100644
index 7598db3f8fe1434..000000000000000
--- a/llvm/lib/Target/RISCV/RISCVMacroFusion.h
+++ /dev/null
@@ -1,28 +0,0 @@
-//===- RISCVMacroFusion.h - RISC-V Macro Fusion -----------------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-/// \file This file contains the RISC-V definition of the DAG scheduling
-/// mutation to pair instructions back to back.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACROFUSION_H
-#define LLVM_LIB_TARGET_RISCV_RISCVMACROFUSION_H
-
-#include "llvm/CodeGen/MachineScheduler.h"
-
-namespace llvm {
-
-/// Note that you have to add:
-/// DAG.addMutation(createRISCVMacroFusionDAGMutation());
-/// to RISCVPassConfig::createMachineScheduler() to have an effect.
-std::unique_ptr<ScheduleDAGMutation> createRISCVMacroFusionDAGMutation();
-
-} // namespace llvm
-
-#endif
diff --git a/llvm/lib/Target/RISCV/RISCVMacroFusion.td b/llvm/lib/Target/RISCV/RISCVMacroFusion.td
new file mode 100644
index 000000000000000..875a93d09a2c647
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVMacroFusion.td
@@ -0,0 +1,93 @@
+//==----- RISCVMacroFusion.td - Macro Fusion Definitions -----*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// ===---------------------------------------------------------------------===//
+// The following definitions describe the macro fusion predicators.
+
+// Fuse LUI followed by ADDI or ADDIW:
+// rd = imm[31:0] which decomposes to
+// lui rd, imm[31:12]
+// addi(w) rd, rd, imm[11:0]
+def TuneLUIADDIFusion
+ : SimpleFusion<"lui-addi-fusion", "HasLUIADDIFusion",
+ "Enable LUI+ADDI macro fusion",
+ CheckOpcode<[LUI]>,
+ CheckOpcode<[ADDI, ADDIW]>>;
+
+// Fuse AUIPC followed by ADDI:
+// auipc rd, imm20
+// addi rd, rd, imm12
+def TuneAUIPCADDIFusion
+ : SimpleFusion<"auipc-addi-fusion", "HasAUIPCADDIFusion",
+ "Enable AUIPC+ADDI macrofusion",
+ CheckOpcode<[AUIPC]>,
+ CheckOpcode<[ADDI]>>;
+
+// Fuse zero extension of halfword:
+// slli rd, rs1, 48
+// srli rd, rd, 48
+def TuneZExtHFusion
+ : SimpleFusion<"zexth-fusion", "HasZExtHFusion",
+ "Enable SLLI+SRLI to be fused to zero extension of halfword",
+ CheckAll<[
+ CheckOpcode<[SLLI]>,
+ CheckIsImmOperand<2>,
+ CheckImmOperand<2, 48>
+ ]>,
+ CheckAll<[
+ CheckOpcode<[SRLI]>,
+ CheckIsImmOperand<2>,
+ CheckImmOperand<2, 48>
+ ]>>;
+
+// Fuse zero extension of word:
+// slli rd, rs1, 32
+// srli rd, rd, 32
+def TuneZExtWFusion
+ : SimpleFusion<"zextw-fusion", "HasZExtWFusion",
+ "Enable SLLI+SRLI to be fused to zero extension of word",
+ CheckAll<[
+ CheckOpcode<[SLLI]>,
+ CheckIsImmOperand<2>,
+ CheckImmOperand<2, 32>
+ ]>,
+ CheckAll<[
+ CheckOpcode<[SRLI]>,
+ CheckIsImmOperand<2>,
+ CheckImmOperand<2, 32>
+ ]>>;
+
+// Fuse shifted zero extension of word:
+// slli rd, rs1, 32
+// srli rd, rd, x
+// where 0 <= x < 32
+def TuneShiftedZExtWFusion
+ : SimpleFusion<"shifted-zextw-fusion", "HasShiftedZExtWFusion",
+ "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",
+ CheckAll<[
+ CheckOpcode<[SLLI]>,
+ CheckIsImmOperand<2>,
+ CheckImmOperand<2, 32>
+ ]>,
+ CheckAll<[
+ CheckOpcode<[SRLI]>,
+ CheckIsImmOperand<2>,
+ CheckImmOperandRange<2, 0, 31>
+ ]>>;
+
+// Fuse load with add:
+// add rd, rs1, rs2
+// ld rd, 0(rd)
+def TuneLDADDFusion
+ : SimpleFusion<"ld-add-fusion", "HasLDADDFusion", "Enable LD+ADD macrofusion",
+ CheckOpcode<[ADD]>,
+ CheckAll<[
+ CheckOpcode<[LD]>,
+ CheckIsImmOperand<2>,
+ CheckImmOperand<2, 0>
+ ]>>;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 7b64d3cee9c8009..d3236bb07d56d53 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -16,8 +16,9 @@
#include "GISel/RISCVRegisterBankInfo.h"
#include "RISCV.h"
#include "RISCVFrameLowering.h"
-#include "RISCVMacroFusion.h"
#include "RISCVTargetMachine.h"
+#include "llvm/CodeGen/MacroFusion.h"
+#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
@@ -29,6 +30,9 @@ using namespace llvm;
#define GET_SUBTARGETINFO_CTOR
#include "RISCVGenSubtargetInfo.inc"
+#define GET_RISCV_MACRO_FUSION_PRED_IMPL
+#include "RISCVGenMacroFusion.inc"
+
namespace llvm::RISCVTuneInfoTable {
#define GET_RISCVTuneInfoTable_IMPL
@@ -187,7 +191,7 @@ bool RISCVSubtarget::enableSubRegLiveness() const {
void RISCVSubtarget::getPostRAMutations(
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
- Mutations.push_back(createRISCVMacroFusionDAGMutation());
+ Mutations.push_back(createMacroFusionDAGMutation(getMacroFusions()));
}
/// Enable use of alias analysis during code generation (during MI
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 2ba93764facd07d..8c55efa69a6a5ff 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -27,6 +27,9 @@
#include "llvm/Target/TargetMachine.h"
#include <bitset>
+#define GET_RISCV_MACRO_FUSION_PRED_DECL
+#include "RISCVGenMacroFusion.inc"
+
#define GET_SUBTARGETINFO_HEADER
#include "RISCVGenSubtargetInfo.inc"
@@ -196,11 +199,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
return UserReservedRegister[i];
}
- bool hasMacroFusion() const {
- return hasLUIADDIFusion() || hasAUIPCADDIFusion() || hasZExtHFusion() ||
- hasZExtWFusion() || hasShiftedZExtWFusion() || hasLDADDFusion();
- }
-
// Vector codegen related methods.
bool hasVInstructions() const { return HasStdExtZve32x; }
bool hasVInstructionsI64() const { return HasStdExtZve64x; }
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index b4b81b545a54bbd..2285c99d7901007 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -14,7 +14,6 @@
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
-#include "RISCVMacroFusion.h"
#include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h"
#include "TargetInfo/RISCVTargetInfo.h"
@@ -26,6 +25,8 @@
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/MIRParser/MIParser.h"
#include "llvm/CodeGen/MIRYamlMapping.h"
+#include "llvm/CodeGen/MachineScheduler.h"
+#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
@@ -361,9 +362,10 @@ class RISCVPassConfig : public TargetPassConfig {
DAG->addMutation(createLoadClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
}
- if (ST.hasMacroFusion()) {
+ const auto &MacroFusions = ST.getMacroFusions();
+ if (!MacroFusions.empty()) {
DAG = DAG ? DAG : createGenericSchedLive(C);
- DAG->addMutation(createRISCVMacroFusionDAGMutation());
+ DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
}
return DAG;
}
@@ -371,9 +373,10 @@ class RISCVPassConfig : public TargetPassConfig {
ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext *C) const override {
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
- if (ST.hasMacroFusion()) {
+ const auto &MacroFusions = ST.getMacroFusions();
+ if (!MacroFusions.empty()) {
ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
- DAG->addMutation(createRISCVMacroFusionDAGMutation());
+ DAG->addMutation(createMacroFusionDAGMutation(MacroFusions));
return DAG;
}
return nullptr;
More information about the llvm-commits
mailing list