[llvm] [RISCV] Refine cost on Min/Max reduction with i1 type (PR #79401)

[Luke Lau via llvm-commits]

================
@@ -936,10 +936,15 @@ RISCVTTIImpl::getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,
     return BaseT::getMinMaxReductionCost(IID, Ty, FMF, CostKind);
 
   std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
-  if (Ty->getElementType()->isIntegerTy(1))
-    // vcpop sequences, see vreduction-mask.ll.  umax, smin actually only
-    // cost 2, but we don't have enough info here so we slightly over cost.
-    return (LT.first - 1) + 3;
+  if (Ty->getElementType()->isIntegerTy(1)) {
+    // InstCombine does following transform:
----------------
lukel97 wrote:

I ran instcombine on some test examples and it didn't seem to be transforming the reductions. But the incoming selection dag uses `vecreduce_or`/`vecreduce_and` before any sort of legalization. Do you know if this is coming from SelectionDAGBuilder or something?

https://github.com/llvm/llvm-project/pull/79401