[llvm] [InstCombine] Fold (sub (xor X, (sext C)), (sext C)) => (select C (neg X), X) (PR #79417)
Kai Luo via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 24 23:56:02 PST 2024
https://github.com/bzEq created https://github.com/llvm/llvm-project/pull/79417
This is useful when computing absdiff.
Correctness prove: https://alive2.llvm.org/ce/z/eMbxps.
>From 85360d691b8572a1f2d6e42f11dd2694b194507a Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Thu, 25 Jan 2024 07:48:50 +0000
Subject: [PATCH 1/3] Add test
---
llvm/test/CodeGen/AArch64/absdiff.ll | 18 +++++++++++++++
llvm/test/CodeGen/PowerPC/absdiff.ll | 19 ++++++++++++++++
llvm/test/CodeGen/X86/absdiff.ll | 22 +++++++++++++++++++
.../Transforms/InstCombine/sub-xor-cmp.ll | 20 +++++++++++++++++
4 files changed, 79 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/absdiff.ll
create mode 100644 llvm/test/CodeGen/PowerPC/absdiff.ll
create mode 100644 llvm/test/CodeGen/X86/absdiff.ll
create mode 100644 llvm/test/Transforms/InstCombine/sub-xor-cmp.ll
diff --git a/llvm/test/CodeGen/AArch64/absdiff.ll b/llvm/test/CodeGen/AArch64/absdiff.ll
new file mode 100644
index 00000000000000..ca7b5a583cbe51
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/absdiff.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -mtriple=aarch64-linux-gnu -passes=instcombine < %s -o - | llc -mtriple=aarch64-linux-gnu -o - | FileCheck %s
+
+define i64 @absdiff(i64 %0, i64 %1) {
+; CHECK-LABEL: absdiff:
+; CHECK: // %bb.0:
+; CHECK-NEXT: subs x8, x0, x1
+; CHECK-NEXT: csetm x9, lo
+; CHECK-NEXT: cinv x8, x8, lo
+; CHECK-NEXT: sub x0, x8, x9
+; CHECK-NEXT: ret
+ %3 = icmp ult i64 %0, %1
+ %4 = sext i1 %3 to i64
+ %5 = sub i64 %0, %1
+ %6 = xor i64 %5, %4
+ %7 = sub i64 %6, %4
+ ret i64 %7
+}
diff --git a/llvm/test/CodeGen/PowerPC/absdiff.ll b/llvm/test/CodeGen/PowerPC/absdiff.ll
new file mode 100644
index 00000000000000..a26482fc6497b8
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/absdiff.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -mtriple=powerpc64-linux-gnu -passes=instcombine < %s -o - | llc -mtriple=powerpc64-linux-gnu -o - | FileCheck %s
+
+define i64 @absdiff(i64 %0, i64 %1) {
+; CHECK-LABEL: absdiff:
+; CHECK: # %bb.0:
+; CHECK-NEXT: subc 5, 3, 4
+; CHECK-NEXT: subfe 5, 3, 3
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: xor 3, 3, 5
+; CHECK-NEXT: sub 3, 3, 5
+; CHECK-NEXT: blr
+ %3 = icmp ult i64 %0, %1
+ %4 = sext i1 %3 to i64
+ %5 = sub i64 %0, %1
+ %6 = xor i64 %5, %4
+ %7 = sub i64 %6, %4
+ ret i64 %7
+}
diff --git a/llvm/test/CodeGen/X86/absdiff.ll b/llvm/test/CodeGen/X86/absdiff.ll
new file mode 100644
index 00000000000000..46c7b62e43685b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/absdiff.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -mtriple=x86_64-linux-gnu -passes=instcombine < %s -o - | llc -mtriple=x86_64-linux-gnu -o - | FileCheck %s
+
+define i64 @absdiff(i64 %0, i64 %1) {
+; CHECK-LABEL: absdiff:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movq %rdi, %rcx
+; CHECK-NEXT: subq %rsi, %rcx
+; CHECK-NEXT: setb %al
+; CHECK-NEXT: negq %rax
+; CHECK-NEXT: xorq %rcx, %rax
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: adcq $0, %rax
+; CHECK-NEXT: retq
+ %3 = icmp ult i64 %0, %1
+ %4 = sext i1 %3 to i64
+ %5 = sub i64 %0, %1
+ %6 = xor i64 %5, %4
+ %7 = sub i64 %6, %4
+ ret i64 %7
+}
diff --git a/llvm/test/Transforms/InstCombine/sub-xor-cmp.ll b/llvm/test/Transforms/InstCombine/sub-xor-cmp.ll
new file mode 100644
index 00000000000000..0555bc1c365f5a
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/sub-xor-cmp.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i64 @absdiff(i64 %0, i64 %1) {
+; CHECK-LABEL: define i64 @absdiff(
+; CHECK-SAME: i64 [[TMP0:%.*]], i64 [[TMP1:%.*]]) {
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[TMP3]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[TMP6]], [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP7]]
+;
+ %3 = icmp ult i64 %0, %1
+ %4 = sext i1 %3 to i64
+ %5 = sub i64 %0, %1
+ %6 = xor i64 %5, %4
+ %7 = sub i64 %6, %4
+ ret i64 %7
+}
>From 9073811a3b45c6bee911f5af4ec3f9debd09f62f Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Thu, 25 Jan 2024 06:45:33 +0000
Subject: [PATCH 2/3] (sub (xor X, (sext C)), (sext C)) => (select C (neg X),
X)
---
llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index 8a00b75a1f7404..1a13fa4e209994 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -2448,6 +2448,16 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
}
}
+ {
+ // (sub (xor X, (sext C)), (sext C)) => (select C (neg X), X)
+ Value *C0, *C1, *X;
+ if (match(Op0, m_Xor(m_Value(X), m_SExt(m_Value(C0)))) &&
+ (C0->getType()->getScalarSizeInBits() == 1) &&
+ match(Op1, m_SExt(m_Value(C1))) && (C0 == C1)) {
+ return SelectInst::Create(C0, Builder.CreateNeg(X), X);
+ }
+ }
+
if (Instruction *R = tryFoldInstWithCtpopWithNot(&I))
return R;
>From 6ef247174203d4a47e16ed5648fbfade3284ecff Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Thu, 25 Jan 2024 07:52:14 +0000
Subject: [PATCH 3/3] Update test
---
llvm/test/CodeGen/AArch64/absdiff.ll | 4 +---
llvm/test/CodeGen/PowerPC/absdiff.ll | 14 +++++++++-----
llvm/test/CodeGen/X86/absdiff.ll | 11 ++++-------
llvm/test/Transforms/InstCombine/sub-xor-cmp.ll | 9 ++++-----
4 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/absdiff.ll b/llvm/test/CodeGen/AArch64/absdiff.ll
index ca7b5a583cbe51..88c6fdad0a2030 100644
--- a/llvm/test/CodeGen/AArch64/absdiff.ll
+++ b/llvm/test/CodeGen/AArch64/absdiff.ll
@@ -5,9 +5,7 @@ define i64 @absdiff(i64 %0, i64 %1) {
; CHECK-LABEL: absdiff:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, x1
-; CHECK-NEXT: csetm x9, lo
-; CHECK-NEXT: cinv x8, x8, lo
-; CHECK-NEXT: sub x0, x8, x9
+; CHECK-NEXT: cneg x0, x8, lo
; CHECK-NEXT: ret
%3 = icmp ult i64 %0, %1
%4 = sext i1 %3 to i64
diff --git a/llvm/test/CodeGen/PowerPC/absdiff.ll b/llvm/test/CodeGen/PowerPC/absdiff.ll
index a26482fc6497b8..c806da988f0a0b 100644
--- a/llvm/test/CodeGen/PowerPC/absdiff.ll
+++ b/llvm/test/CodeGen/PowerPC/absdiff.ll
@@ -4,11 +4,15 @@
define i64 @absdiff(i64 %0, i64 %1) {
; CHECK-LABEL: absdiff:
; CHECK: # %bb.0:
-; CHECK-NEXT: subc 5, 3, 4
-; CHECK-NEXT: subfe 5, 3, 3
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: xor 3, 3, 5
-; CHECK-NEXT: sub 3, 3, 5
+; CHECK-NEXT: sub 5, 3, 4
+; CHECK-NEXT: neg 6, 5
+; CHECK-NEXT: cmpld 3, 4
+; CHECK-NEXT: bc 12, 0, .LBB0_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ori 3, 5, 0
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT: addi 3, 6, 0
; CHECK-NEXT: blr
%3 = icmp ult i64 %0, %1
%4 = sext i1 %3 to i64
diff --git a/llvm/test/CodeGen/X86/absdiff.ll b/llvm/test/CodeGen/X86/absdiff.ll
index 46c7b62e43685b..ce9a0093544813 100644
--- a/llvm/test/CodeGen/X86/absdiff.ll
+++ b/llvm/test/CodeGen/X86/absdiff.ll
@@ -4,14 +4,11 @@
define i64 @absdiff(i64 %0, i64 %1) {
; CHECK-LABEL: absdiff:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: movq %rdi, %rcx
-; CHECK-NEXT: subq %rsi, %rcx
-; CHECK-NEXT: setb %al
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: subq %rsi, %rax
; CHECK-NEXT: negq %rax
-; CHECK-NEXT: xorq %rcx, %rax
-; CHECK-NEXT: cmpq %rsi, %rdi
-; CHECK-NEXT: adcq $0, %rax
+; CHECK-NEXT: subq %rsi, %rdi
+; CHECK-NEXT: cmovaeq %rdi, %rax
; CHECK-NEXT: retq
%3 = icmp ult i64 %0, %1
%4 = sext i1 %3 to i64
diff --git a/llvm/test/Transforms/InstCombine/sub-xor-cmp.ll b/llvm/test/Transforms/InstCombine/sub-xor-cmp.ll
index 0555bc1c365f5a..393f2bd45bb8d7 100644
--- a/llvm/test/Transforms/InstCombine/sub-xor-cmp.ll
+++ b/llvm/test/Transforms/InstCombine/sub-xor-cmp.ll
@@ -5,11 +5,10 @@ define i64 @absdiff(i64 %0, i64 %1) {
; CHECK-LABEL: define i64 @absdiff(
; CHECK-SAME: i64 [[TMP0:%.*]], i64 [[TMP1:%.*]]) {
; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[TMP3]] to i64
-; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], [[TMP4]]
-; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[TMP6]], [[TMP4]]
-; CHECK-NEXT: ret i64 [[TMP7]]
+; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = sub i64 0, [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP3]], i64 [[TMP5]], i64 [[TMP4]]
+; CHECK-NEXT: ret i64 [[TMP6]]
;
%3 = icmp ult i64 %0, %1
%4 = sext i1 %3 to i64
More information about the llvm-commits
mailing list