[llvm] [X86] Support APX promoted RAO-INT and MOVBE instructions (PR #77431)

[via llvm-commits]

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@@ -25,21 +25,26 @@ def X86rao_xor  : SDNode<"X86ISD::AXOR", SDTRAOBinaryArith,
 def X86rao_and  : SDNode<"X86ISD::AAND", SDTRAOBinaryArith,
                          [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
-multiclass RAOINT_BASE<string OpcodeStr> {
-  let Predicates = [HasRAOINT] in
-    def 32mr : I<0xfc, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
-                 !strconcat("a", OpcodeStr, "{l}\t{$src, $dst|$dst, $src}"),
-                 [(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR32:$src)]>,
-               Sched<[WriteALURMW]>;
+multiclass RaoInt<string m, string suffix = ""> {
+  let SchedRW = [WriteALURMW, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault] in {
+    def 32mr#suffix : BinOpMR<0xfc, "a"#m, binop_args, Xi32, (outs),
+                        [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR32:$src2)]>;
 
-  let Predicates = [HasRAOINT, In64BitMode] in
-    def 64mr : I<0xfc, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
-                 !strconcat("a", OpcodeStr, "{q}\t{$src, $dst|$dst, $src}"),
-                 [(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR64:$src)]>,
-               Sched<[WriteALURMW]>, REX_W;
+    def 64mr#suffix : BinOpMR<0xfc, "a"#m, binop_args, Xi64, (outs),
+                        [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR64:$src2)]>, REX_W;
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XinWang10 wrote:

BinOpMR_M has no pattern.

https://github.com/llvm/llvm-project/pull/77431