[llvm] 5446902 - [RISCV] Add IsSignExtendingOpW to amocas.w. (#79351)

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-01-24T20:15:41-08:00
New Revision: 5446902cf2cda4fb17078d04207d2544518a49be

URL: https://github.com/llvm/llvm-project/commit/5446902cf2cda4fb17078d04207d2544518a49be
DIFF: https://github.com/llvm/llvm-project/commit/5446902cf2cda4fb17078d04207d2544518a49be.diff

LOG: [RISCV] Add IsSignExtendingOpW to amocas.w. (#79351)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
    llvm/test/CodeGen/RISCV/atomic-signext.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
index ffcdd0010749389..6b7f31d465e2002 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
@@ -54,7 +54,7 @@ multiclass AMO_cas_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr,
   def _AQ_RL : AMO_cas<funct5, 1, 1, funct3, opcodestr # ".aqrl", RC>;
 }
 
-let Predicates = [HasStdExtZacas] in {
+let Predicates = [HasStdExtZacas], IsSignExtendingOpW = 1 in {
 defm AMOCAS_W : AMO_cas_aq_rl<0b00101, 0b010, "amocas.w", GPR>;
 } // Predicates = [HasStdExtZacas]
 

diff  --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll
index f1f8bffb381faae..9cfb94472396770 100644
--- a/llvm/test/CodeGen/RISCV/atomic-signext.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll
@@ -5525,11 +5525,10 @@ define signext i32 @cmpxchg_i32_monotonic_crossbb(ptr %ptr, i32 signext %cmp, i3
 ; RV64IA-ZACAS-NEXT:    beqz a3, .LBB64_2
 ; RV64IA-ZACAS-NEXT:  # %bb.1: # %then
 ; RV64IA-ZACAS-NEXT:    amocas.w.aqrl a1, a2, (a0)
-; RV64IA-ZACAS-NEXT:    sext.w a0, a1
+; RV64IA-ZACAS-NEXT:    mv a0, a1
 ; RV64IA-ZACAS-NEXT:    ret
 ; RV64IA-ZACAS-NEXT:  .LBB64_2: # %else
-; RV64IA-ZACAS-NEXT:    lw a1, 0(a0)
-; RV64IA-ZACAS-NEXT:    sext.w a0, a1
+; RV64IA-ZACAS-NEXT:    lw a0, 0(a0)
 ; RV64IA-ZACAS-NEXT:    ret
   br i1 %c, label %then, label %else