[llvm] fd81724 - [RISCV] Sink code into using branch in shuffle lowering [nfc]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 24 08:52:15 PST 2024
Author: Philip Reames
Date: 2024-01-24T08:52:07-08:00
New Revision: fd817249f4d50caa7a8986a37cdf712dfdf5ad70
URL: https://github.com/llvm/llvm-project/commit/fd817249f4d50caa7a8986a37cdf712dfdf5ad70
DIFF: https://github.com/llvm/llvm-project/commit/fd817249f4d50caa7a8986a37cdf712dfdf5ad70.diff
LOG: [RISCV] Sink code into using branch in shuffle lowering [nfc]
Follow up to 396b6bbc, sink code into consuming branch, and fix one
comment I realized used the misleading wording. (Permute is a specific
sub-type of single source shuffle.)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5d61baae0ce4eb9..a38352e8e87f21c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4998,32 +4998,32 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
MVT MaskVT = MVT::getVectorVT(MVT::i1, NumElts);
SDValue SelectMask = DAG.getBuildVector(MaskVT, DL, MaskVals);
- unsigned GatherVVOpc = RISCVISD::VRGATHER_VV_VL;
- MVT IndexVT = VT.changeTypeToInteger();
- // Since we can't introduce illegal index types at this stage, use i16 and
- // vrgatherei16 if the corresponding index type for plain vrgather is greater
- // than XLenVT.
- if (IndexVT.getScalarType().bitsGT(XLenVT)) {
- GatherVVOpc = RISCVISD::VRGATHEREI16_VV_VL;
- IndexVT = IndexVT.changeVectorElementType(MVT::i16);
- }
-
- // If the mask allows, we can do all the index computation in 16 bits. This
- // requires less work and less register pressure at high LMUL, and creates
- // smaller constants which may be cheaper to materialize.
- if (IndexVT.getScalarType().bitsGT(MVT::i16) && isUInt<16>(NumElts - 1) &&
- (IndexVT.getSizeInBits() / Subtarget.getRealMinVLen()) > 1) {
- GatherVVOpc = RISCVISD::VRGATHEREI16_VV_VL;
- IndexVT = IndexVT.changeVectorElementType(MVT::i16);
- }
-
- MVT IndexContainerVT =
- ContainerVT.changeVectorElementType(IndexVT.getScalarType());
-
// Base case for the recursion just below - handle the worst case
// single source permutation. Note that all the splat variants
// are handled above.
if (V2.isUndef()) {
+ unsigned GatherVVOpc = RISCVISD::VRGATHER_VV_VL;
+ MVT IndexVT = VT.changeTypeToInteger();
+ // Since we can't introduce illegal index types at this stage, use i16 and
+ // vrgatherei16 if the corresponding index type for plain vrgather is greater
+ // than XLenVT.
+ if (IndexVT.getScalarType().bitsGT(XLenVT)) {
+ GatherVVOpc = RISCVISD::VRGATHEREI16_VV_VL;
+ IndexVT = IndexVT.changeVectorElementType(MVT::i16);
+ }
+
+ // If the mask allows, we can do all the index computation in 16 bits. This
+ // requires less work and less register pressure at high LMUL, and creates
+ // smaller constants which may be cheaper to materialize.
+ if (IndexVT.getScalarType().bitsGT(MVT::i16) && isUInt<16>(NumElts - 1) &&
+ (IndexVT.getSizeInBits() / Subtarget.getRealMinVLen()) > 1) {
+ GatherVVOpc = RISCVISD::VRGATHEREI16_VV_VL;
+ IndexVT = IndexVT.changeVectorElementType(MVT::i16);
+ }
+
+ MVT IndexContainerVT =
+ ContainerVT.changeVectorElementType(IndexVT.getScalarType());
+
V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget);
SmallVector<SDValue> GatherIndicesLHS;
for (int ShuffleIdx : ShuffleMaskLHS)
@@ -5039,7 +5039,7 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
}
// Recursively invoke lowering for each operand if we had two
- // independent single source permutes, and then combine the result via a
+ // independent single source shuffles, and then combine the result via a
// vselect. Note that the vselect will likely be folded back into the
// second permute (vrgather, or other) by the post-isel combine.
V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), ShuffleMaskLHS);
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