[llvm] [AMDGPU][NFC] Simplify AGPR/VGPR load/store operand definitions. (PR #79289)
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 24 05:42:58 PST 2024
https://github.com/kosarev created https://github.com/llvm/llvm-project/pull/79289
Part of <https://github.com/llvm/llvm-project/issues/62629>.
>From 415ab464f47b449989568ce325a36740c957c69b Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Wed, 24 Jan 2024 13:37:49 +0000
Subject: [PATCH] [AMDGPU][NFC] Simplify AGPR/VGPR load/store operand
definitions.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
---
.../Disassembler/AMDGPUDisassembler.cpp | 48 ++++---------------
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 29 ++++-------
2 files changed, 18 insertions(+), 59 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 2c6aa2ee348a1f2..38ba87f6691f90b 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -361,9 +361,9 @@ static bool IsAGPROperand(const MCInst &Inst, int OpIdx,
return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
}
-static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm,
- AMDGPUDisassembler::OpWidthTy Opw,
- const MCDisassembler *Decoder) {
+static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
+ AMDGPUDisassembler::OpWidthTy Opw,
+ const MCDisassembler *Decoder) {
auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
if (!DAsm->isGFX90A()) {
Imm &= 511;
@@ -395,6 +395,13 @@ static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm,
return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
}
+template <AMDGPUDisassembler::OpWidthTy Opw>
+static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
+ uint64_t /* Addr */,
+ const MCDisassembler *Decoder) {
+ return decodeAVLdSt(Inst, Imm, Opw, Decoder);
+}
+
static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm,
uint64_t Addr,
const MCDisassembler *Decoder) {
@@ -404,41 +411,6 @@ static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm,
Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true));
}
-static DecodeStatus
-DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,
- const MCDisassembler *Decoder) {
- return decodeOperand_AVLdSt_Any(Inst, Imm,
- AMDGPUDisassembler::OPW32, Decoder);
-}
-
-static DecodeStatus
-DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,
- const MCDisassembler *Decoder) {
- return decodeOperand_AVLdSt_Any(Inst, Imm,
- AMDGPUDisassembler::OPW64, Decoder);
-}
-
-static DecodeStatus
-DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,
- const MCDisassembler *Decoder) {
- return decodeOperand_AVLdSt_Any(Inst, Imm,
- AMDGPUDisassembler::OPW96, Decoder);
-}
-
-static DecodeStatus
-DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,
- const MCDisassembler *Decoder) {
- return decodeOperand_AVLdSt_Any(Inst, Imm,
- AMDGPUDisassembler::OPW128, Decoder);
-}
-
-static DecodeStatus
-DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,
- const MCDisassembler *Decoder) {
- return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160,
- Decoder);
-}
-
#define DECODE_SDWA(DecName) \
DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index f42af89cf5e6d37..01c4296419fb807 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1379,30 +1379,17 @@ def AVDst_512 : RegisterOperand<AV_512> {
let EncoderMethod = "getAVOperandEncoding";
}
-def AVLdSt_32 : RegisterOperand<AV_32> {
- let DecoderMethod = "DecodeAVLdSt_32RegisterClass";
+class AVLdStOperand<RegisterClass regClass, string width>
+ : RegisterOperand<regClass> {
+ let DecoderMethod = "decodeAVLdSt<AMDGPUDisassembler::" # width # ">";
let EncoderMethod = "getAVOperandEncoding";
}
-def AVLdSt_64 : RegisterOperand<AV_64> {
- let DecoderMethod = "DecodeAVLdSt_64RegisterClass";
- let EncoderMethod = "getAVOperandEncoding";
-}
-
-def AVLdSt_96 : RegisterOperand<AV_96> {
- let DecoderMethod = "DecodeAVLdSt_96RegisterClass";
- let EncoderMethod = "getAVOperandEncoding";
-}
-
-def AVLdSt_128 : RegisterOperand<AV_128> {
- let DecoderMethod = "DecodeAVLdSt_128RegisterClass";
- let EncoderMethod = "getAVOperandEncoding";
-}
-
-def AVLdSt_160 : RegisterOperand<AV_160> {
- let DecoderMethod = "DecodeAVLdSt_160RegisterClass";
- let EncoderMethod = "getAVOperandEncoding";
-}
+def AVLdSt_32 : AVLdStOperand<AV_32, "OPW32">;
+def AVLdSt_64 : AVLdStOperand<AV_64, "OPW64">;
+def AVLdSt_96 : AVLdStOperand<AV_96, "OPW96">;
+def AVLdSt_128 : AVLdStOperand<AV_128, "OPW128">;
+def AVLdSt_160 : AVLdStOperand<AV_160, "OPW160">;
//===----------------------------------------------------------------------===//
// ACSrc_* Operands with an AGPR or an inline constant
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