[llvm] [AMDGPU][AsmParser][NFC] Rename integer modifier operands to follow the convention. (PR #79284)
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 24 05:06:56 PST 2024
https://github.com/kosarev created https://github.com/llvm/llvm-project/pull/79284
Part of <https://github.com/llvm/llvm-project/issues/62629>.
>From 1fa35edeabe7dd70e633daf4119ffc056026d4bc Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Wed, 24 Jan 2024 12:22:59 +0000
Subject: [PATCH] [AMDGPU][AsmParser][NFC] Rename integer modifier operands to
follow the convention.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
---
llvm/lib/Target/AMDGPU/BUFInstructions.td | 16 +++---
llvm/lib/Target/AMDGPU/DSDIRInstructions.td | 10 ++--
llvm/lib/Target/AMDGPU/DSInstructions.td | 50 +++++++++----------
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 46 ++++++++---------
llvm/lib/Target/AMDGPU/VINTERPInstructions.td | 4 +-
llvm/lib/Target/AMDGPU/VOP1Instructions.td | 6 +--
llvm/lib/Target/AMDGPU/VOP2Instructions.td | 38 +++++++-------
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 16 +++---
llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 14 +++---
llvm/lib/Target/AMDGPU/VOPCInstructions.td | 4 +-
10 files changed, 102 insertions(+), 102 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index ae0955f0cf6a4d..a180dd5759d6f9 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -163,7 +163,7 @@ class getMTBUFInsDA<list<RegisterClass> vdataList,
(ins SCSrc_b32:$soffset));
dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset,
- (ins offset:$offset, FORMAT:$format, CPol_0:$cpol, i1imm_0:$swz));
+ (ins Offset:$offset, FORMAT:$format, CPol_0:$cpol, i1imm_0:$swz));
dag Inputs = !if(!empty(vaddrList),
NonVaddrInputs,
@@ -410,7 +410,7 @@ class getMUBUFInsDA<list<RegisterClass> vdataList,
RegisterOperand vdata_op = getLdStVDataRegisterOperand<vdataClass, isTFE>.ret;
dag SOffset = !if(hasGFX12Enc, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
- dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset, (ins offset:$offset, CPol_0:$cpol, i1imm_0:$swz));
+ dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset, (ins Offset:$offset, CPol_0:$cpol, i1imm_0:$swz));
dag Inputs = !if(!empty(vaddrList), NonVaddrInputs, !con((ins vaddrClass:$vaddr), NonVaddrInputs));
dag ret = !if(!empty(vdataList), Inputs, !con((ins vdata_op:$vdata), Inputs));
@@ -664,7 +664,7 @@ multiclass MUBUF_Pseudo_Stores<string opName, ValueType store_vt = i32> {
class MUBUF_Pseudo_Store_Lds<string opName>
: MUBUF_Pseudo<opName,
(outs),
- (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol:$cpol, i1imm:$swz),
+ (ins SReg_128:$srsrc, SCSrc_b32:$soffset, Offset:$offset, CPol:$cpol, i1imm:$swz),
" $srsrc, $soffset$offset lds$cpol"> {
let LGKM_CNT = 1;
let mayLoad = 1;
@@ -687,7 +687,7 @@ class getMUBUFAtomicInsDA<RegisterClass vdataClass, bit vdata_in, bit hasGFX12En
dag VData = !if(vdata_in, (ins vdata_op:$vdata_in), (ins vdata_op:$vdata));
dag Data = !if(!empty(vaddrList), VData, !con(VData, (ins vaddrClass:$vaddr)));
dag SOffset = !if(hasGFX12Enc, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
- dag MainInputs = !con((ins SReg_128:$srsrc), SOffset, (ins offset:$offset));
+ dag MainInputs = !con((ins SReg_128:$srsrc), SOffset, (ins Offset:$offset));
dag CPol = !if(vdata_in, (ins CPol_GLC_WithDefault:$cpol),
(ins CPol_NonGLC_WithDefault:$cpol));
@@ -1537,14 +1537,14 @@ multiclass BufferAtomicPat_Common<string OpPrefix, ValueType vt, string Inst, bi
def : GCNPat<
(vt (Op (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset), vt:$vdata_in)),
(!cast<MUBUF_Pseudo>(Inst # "_OFFSET" # InstSuffix) getVregSrcForVT<vt>.ret:$vdata_in,
- SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset)
+ SReg_128:$srsrc, SCSrc_b32:$soffset, Offset:$offset)
>;
def : GCNPat<
(vt (Op (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i32:$offset),
vt:$vdata_in)),
(!cast<MUBUF_Pseudo>(Inst # "_ADDR64" # InstSuffix) getVregSrcForVT<vt>.ret:$vdata_in,
- VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset)
+ VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset, Offset:$offset)
>;
} // end let AddedComplexity
@@ -1574,7 +1574,7 @@ multiclass BufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, string
let AddedComplexity = !if(!eq(RtnMode, "ret"), 0, 1) in {
defvar OffsetResDag = (!cast<MUBUF_Pseudo>(Inst # "_OFFSET" # InstSuffix)
data_vt_RC:$vdata_in, SReg_128:$srsrc, SCSrc_b32:$soffset,
- offset:$offset);
+ Offset:$offset);
def : GCNPat<
(vt (Op (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset), data_vt:$vdata_in)),
!if(!eq(RtnMode, "ret"),
@@ -1585,7 +1585,7 @@ multiclass BufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, string
defvar Addr64ResDag = (!cast<MUBUF_Pseudo>(Inst # "_ADDR64" # InstSuffix)
data_vt_RC:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
- SCSrc_b32:$soffset, offset:$offset);
+ SCSrc_b32:$soffset, Offset:$offset);
def : GCNPat<
(vt (Op (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i32:$offset),
data_vt:$vdata_in)),
diff --git a/llvm/lib/Target/AMDGPU/DSDIRInstructions.td b/llvm/lib/Target/AMDGPU/DSDIRInstructions.td
index 4416da60598131..757845ae2b7a03 100644
--- a/llvm/lib/Target/AMDGPU/DSDIRInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSDIRInstructions.td
@@ -52,16 +52,16 @@ class VDSDIRe<bits<2> op, bit is_direct> : Enc32 {
class LDSDIR_getIns<bit direct> {
dag ret = !if(direct,
- (ins wait_vdst:$waitvdst),
- (ins InterpAttr:$attr, InterpAttrChan:$attrchan, wait_vdst:$waitvdst)
+ (ins WaitVDST:$waitvdst),
+ (ins InterpAttr:$attr, InterpAttrChan:$attrchan, WaitVDST:$waitvdst)
);
}
class VDSDIR_getIns<bit direct> {
dag ret = !if(direct,
- (ins wait_va_vdst:$waitvdst, wait_va_vsrc:$waitvsrc),
- (ins InterpAttr:$attr, InterpAttrChan:$attrchan, wait_va_vdst:$waitvdst,
- wait_va_vsrc:$waitvsrc)
+ (ins WaitVAVDst:$waitvdst, WaitVMVSrc:$waitvsrc),
+ (ins InterpAttr:$attr, InterpAttrChan:$attrchan, WaitVAVDst:$waitvdst,
+ WaitVMVSrc:$waitvsrc)
);
}
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index d09e1ef3bcb27a..0888fb84a22fa6 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -95,7 +95,7 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs),
- (ins getLdStRegisterOperand<rc>.ret:$data0, offset:$offset, gds:$gds),
+ (ins getLdStRegisterOperand<rc>.ret:$data0, Offset:$offset, gds:$gds),
" $data0$offset$gds"> {
let has_addr = 0;
@@ -106,7 +106,7 @@ class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs),
- (ins VGPR_32:$addr, getLdStRegisterOperand<rc>.ret:$data0, offset:$offset, gds:$gds),
+ (ins VGPR_32:$addr, getLdStRegisterOperand<rc>.ret:$data0, Offset:$offset, gds:$gds),
" $addr, $data0$offset$gds"> {
let has_data1 = 0;
@@ -135,7 +135,7 @@ class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32,
RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
: DS_Pseudo<opName,
(outs),
- (ins VGPR_32:$addr, data_op:$data0, data_op:$data1, offset:$offset, gds:$gds),
+ (ins VGPR_32:$addr, data_op:$data0, data_op:$data1, Offset:$offset, gds:$gds),
" $addr, $data0, $data1$offset$gds"> {
let has_vdst = 0;
@@ -157,7 +157,7 @@ class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32,
: DS_Pseudo<opName,
(outs),
(ins VGPR_32:$addr, data_op:$data0, data_op:$data1,
- offset0:$offset0, offset1:$offset1, gds:$gds),
+ Offset0:$offset0, Offset1:$offset1, gds:$gds),
" $addr, $data0, $data1$offset0$offset1$gds"> {
let has_vdst = 0;
@@ -177,7 +177,7 @@ class DS_0A1D_RET_GDS<string opName, RegisterClass rc = VGPR_32, RegisterClass s
RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
: DS_Pseudo<opName,
(outs dst_op:$vdst),
- (ins src_op:$data0, offset:$offset),
+ (ins src_op:$data0, Offset:$offset),
" $vdst, $data0$offset gds"> {
let has_addr = 0;
@@ -191,7 +191,7 @@ class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32,
RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
: DS_Pseudo<opName,
(outs data_op:$vdst),
- (ins VGPR_32:$addr, data_op:$data0, offset:$offset, gds:$gds),
+ (ins VGPR_32:$addr, data_op:$data0, Offset:$offset, gds:$gds),
" $vdst, $addr, $data0$offset$gds"> {
let hasPostISelHook = 1;
@@ -227,7 +227,7 @@ class DS_1A2D_RET<string opName,
RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
: DS_Pseudo<opName,
(outs dst_op:$vdst),
- (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, offset:$offset, gds:$gds),
+ (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, Offset:$offset, gds:$gds),
" $vdst, $addr, $data0, $data1$offset$gds"> {
let hasPostISelHook = 1;
@@ -254,7 +254,7 @@ class DS_1A2D_Off8_RET<string opName,
RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
: DS_Pseudo<opName,
(outs dst_op:$vdst),
- (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
+ (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, Offset0:$offset0, Offset1:$offset1, gds:$gds),
" $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
let has_offset = 0;
@@ -274,7 +274,7 @@ multiclass DS_1A2D_Off8_RET_mc<string opName,
class DS_BVH_STACK<string opName>
: DS_Pseudo<opName,
(outs getLdStRegisterOperand<VGPR_32>.ret:$vdst, VGPR_32:$addr),
- (ins VGPR_32:$addr_in, getLdStRegisterOperand<VGPR_32>.ret:$data0, VReg_128:$data1, offset:$offset),
+ (ins VGPR_32:$addr_in, getLdStRegisterOperand<VGPR_32>.ret:$data0, VReg_128:$data1, Offset:$offset),
" $vdst, $addr, $data0, $data1$offset"> {
let Constraints = "$addr = $addr_in";
let DisableEncoding = "$addr_in";
@@ -285,7 +285,7 @@ class DS_BVH_STACK<string opName>
let SchedRW = [WriteLDS, WriteLDS];
}
-class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset,
+class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = Offset,
RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
: DS_Pseudo<opName,
(outs data_op:$vdst),
@@ -299,7 +299,7 @@ class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0
let has_data1 = 0;
}
-multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
+multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = Offset> {
def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
let has_m0_read = 0 in {
@@ -313,7 +313,7 @@ class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs getLdStRegisterOperand<rc>.ret:$vdst),
- (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
+ (ins VGPR_32:$addr, Offset0:$offset0, Offset1:$offset1, gds:$gds),
" $vdst, $addr$offset0$offset1$gds"> {
let has_offset = 0;
@@ -331,7 +331,7 @@ multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
(outs getLdStRegisterOperand<VGPR_32>.ret:$vdst),
- (ins VGPR_32:$addr, offset:$offset),
+ (ins VGPR_32:$addr, Offset:$offset),
" $vdst, $addr$offset gds"> {
let has_data0 = 0;
@@ -342,7 +342,7 @@ class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
class DS_0A_RET <string opName> : DS_Pseudo<opName,
(outs getLdStRegisterOperand<VGPR_32>.ret:$vdst),
- (ins offset:$offset, gds:$gds),
+ (ins Offset:$offset, gds:$gds),
" $vdst$offset$gds"> {
let mayLoad = 1;
@@ -355,7 +355,7 @@ class DS_0A_RET <string opName> : DS_Pseudo<opName,
class DS_1A <string opName> : DS_Pseudo<opName,
(outs),
- (ins VGPR_32:$addr, offset:$offset, gds:$gds),
+ (ins VGPR_32:$addr, Offset:$offset, gds:$gds),
" $addr$offset$gds"> {
let mayLoad = 1;
@@ -390,13 +390,13 @@ class DS_GWS <string opName, dag ins, string asmOps>
class DS_GWS_0D <string opName>
: DS_GWS<opName,
- (ins offset:$offset), "$offset gds"> {
+ (ins Offset:$offset), "$offset gds"> {
let hasSideEffects = 1;
}
class DS_GWS_1D <string opName>
: DS_GWS<opName,
- (ins getLdStRegisterOperand<VGPR_32>.ret:$data0, offset:$offset),
+ (ins getLdStRegisterOperand<VGPR_32>.ret:$data0, Offset:$offset),
" $data0$offset gds"> {
let has_gws_data0 = 1;
@@ -424,7 +424,7 @@ class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag,
RegisterOperand data_op = getLdStRegisterOperand<VGPR_32>.ret>
: DS_Pseudo<opName,
(outs data_op:$vdst),
- (ins VGPR_32:$addr, data_op:$data0, offset:$offset),
+ (ins VGPR_32:$addr, data_op:$data0, Offset:$offset),
" $vdst, $addr, $data0$offset",
[(set i32:$vdst,
(node (DS1Addr1Offset i32:$addr, i32:$offset), i32:$data0))] > {
@@ -439,7 +439,7 @@ class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag,
class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag, int complexity = 0,
bit gds=0> : GCNPat <(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
- (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))> {
+ (inst $ptr, getVregSrcForVT<vt>.ret:$value, Offset:$offset, (i1 gds))> {
let AddedComplexity = complexity;
}
@@ -767,7 +767,7 @@ def : GCNPat <
class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
(vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
- (inst $ptr, offset:$offset, (i1 gds))
+ (inst $ptr, Offset:$offset, (i1 gds))
>;
multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
@@ -783,7 +783,7 @@ multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
class DSReadPat_D16 <DS_Pseudo inst, PatFrag frag, ValueType vt> : GCNPat <
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$in),
- (inst $ptr, offset:$offset, (i1 0), $in)
+ (inst $ptr, Offset:$offset, (i1 0), $in)
>;
defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">;
@@ -827,7 +827,7 @@ def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
(frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
- (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
+ (inst $ptr, getVregSrcForVT<vt>.ret:$value, Offset:$offset, (i1 gds))
>;
multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
@@ -1022,7 +1022,7 @@ let SubtargetPredicate = isGFX6GFX7GFX8GFX9GFX10 in {
class DSAtomicCmpXChgSwapped<DS_Pseudo inst, ValueType vt, PatFrag frag,
int complexity = 0, bit gds=0> : GCNPat<
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
- (inst $ptr, getVregSrcForVT<vt>.ret:$cmp, getVregSrcForVT<vt>.ret:$swap, offset:$offset, (i1 gds))> {
+ (inst $ptr, getVregSrcForVT<vt>.ret:$cmp, getVregSrcForVT<vt>.ret:$swap, Offset:$offset, (i1 gds))> {
let AddedComplexity = complexity;
}
@@ -1056,7 +1056,7 @@ let SubtargetPredicate = isGFX11Plus in {
class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag,
int complexity = 0, bit gds=0> : GCNPat<
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
- (inst $ptr, getVregSrcForVT<vt>.ret:$swap, getVregSrcForVT<vt>.ret:$cmp, offset:$offset, (i1 gds))> {
+ (inst $ptr, getVregSrcForVT<vt>.ret:$swap, getVregSrcForVT<vt>.ret:$cmp, Offset:$offset, (i1 gds))> {
let AddedComplexity = complexity;
}
@@ -1136,7 +1136,7 @@ def : DSAtomicRetPat<DS_ADD_F64, f64, atomic_load_fadd_local_noret_64>;
class DSAtomicRetPatIntrinsic<DS_Pseudo inst, ValueType vt, PatFrag frag,
bit gds=0> : GCNPat <
(vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value)),
- (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))> {
+ (inst $ptr, getVregSrcForVT<vt>.ret:$value, Offset:$offset, (i1 gds))> {
}
def : DSAtomicRetPatIntrinsic<DS_ADD_RTN_F64, f64, int_amdgcn_flat_atomic_fadd_local_addrspace>;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 903a04718b6446..03f93818104dcd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -995,8 +995,8 @@ def SDWAVopcDst : BoolRC {
}
class NamedIntOperand<ValueType Type, string Prefix, bit Optional = 1,
- string Name = NAME, string ConvertMethod = "nullptr">
- : CustomOperand<Type, Optional, Name> {
+ string ConvertMethod = "nullptr">
+ : CustomOperand<Type, Optional, NAME> {
let ParserMethod =
"[this](OperandVector &Operands) -> ParseStatus { "#
"return parseIntWithPrefix(\""#Prefix#"\", Operands, "#
@@ -1039,9 +1039,9 @@ class ArrayOperand0<string Id, string Name = NAME>
let ImmTy = "ImmTyOffset" in
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
-def offset : NamedIntOperand<i32, "offset", 1, "Offset">;
-def offset0 : NamedIntOperand<i8, "offset0", 1, "Offset0">;
-def offset1 : NamedIntOperand<i8, "offset1", 1, "Offset1">;
+def Offset : NamedIntOperand<i32, "offset">;
+def Offset0 : NamedIntOperand<i8, "offset0">;
+def Offset1 : NamedIntOperand<i8, "offset1">;
def gds : NamedBitOperand<"gds", "GDS">;
@@ -1092,25 +1092,25 @@ def dpp8 : CustomOperand<i32, 0, "DPP8">;
def dpp_ctrl : CustomOperand<i32, 0, "DPPCtrl">;
let DefaultValue = "0xf" in {
-def row_mask : NamedIntOperand<i32, "row_mask", 1, "DppRowMask">;
-def bank_mask : NamedIntOperand<i32, "bank_mask", 1, "DppBankMask">;
+def DppRowMask : NamedIntOperand<i32, "row_mask">;
+def DppBankMask : NamedIntOperand<i32, "bank_mask">;
}
-def bound_ctrl : NamedIntOperand<i1, "bound_ctrl", 1, "DppBoundCtrl",
+def DppBoundCtrl : NamedIntOperand<i1, "bound_ctrl", 1,
"[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }">;
-def FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
+def DppFI : NamedIntOperand<i32, "fi">;
def blgp : CustomOperand<i32, 1, "BLGP">;
-def cbsz : NamedIntOperand<i32, "cbsz", 1, "CBSZ">;
-def abid : NamedIntOperand<i32, "abid", 1, "ABID">;
+def CBSZ : NamedIntOperand<i32, "cbsz">;
+def ABID : NamedIntOperand<i32, "abid">;
def hwreg : CustomOperand<i32, 0, "Hwreg">;
def exp_tgt : CustomOperand<i32, 0, "ExpTgt">;
-def wait_vdst : NamedIntOperand<i8, "wait_vdst", 1, "WaitVDST">;
-def wait_exp : NamedIntOperand<i8, "wait_exp", 1, "WaitEXP">;
-def wait_va_vdst : NamedIntOperand<i8, "wait_va_vdst", 1, "WaitVAVDst">;
-def wait_va_vsrc : NamedIntOperand<i8, "wait_vm_vsrc", 1, "WaitVMVSrc">;
+def WaitVDST : NamedIntOperand<i8, "wait_vdst">;
+def WaitEXP : NamedIntOperand<i8, "wait_exp">;
+def WaitVAVDst : NamedIntOperand<i8, "wait_va_vdst">;
+def WaitVMVSrc : NamedIntOperand<i8, "wait_vm_vsrc">;
class KImmFPOperand<ValueType vt> : ImmOperand<vt> {
let OperandNamespace = "AMDGPU";
@@ -1830,8 +1830,8 @@ class getInsDPP <RegisterOperand OldRC, RegisterOperand Src0RC, RegisterOperand
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOld = 1> {
dag ret = !con(getInsDPPBase<OldRC, Src0RC, Src1RC, Src2RC, NumSrcArgs,
HasModifiers, Src0Mod, Src1Mod, Src2Mod, HasOld>.ret,
- (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl));
+ (ins dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
+ DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl));
}
class getInsDPP16 <RegisterOperand OldRC, RegisterOperand Src0RC, RegisterOperand Src1RC,
@@ -1839,7 +1839,7 @@ class getInsDPP16 <RegisterOperand OldRC, RegisterOperand Src0RC, RegisterOperan
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOld = 1> {
dag ret = !con(getInsDPP<OldRC, Src0RC, Src1RC, Src2RC, NumSrcArgs,
HasModifiers, Src0Mod, Src1Mod, Src2Mod, HasOld>.ret,
- (ins FI:$fi));
+ (ins DppFI:$fi));
}
class getInsDPP8 <RegisterOperand OldRC, RegisterOperand Src0RC, RegisterOperand Src1RC,
@@ -1847,7 +1847,7 @@ class getInsDPP8 <RegisterOperand OldRC, RegisterOperand Src0RC, RegisterOperand
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOld = 1> {
dag ret = !con(getInsDPPBase<OldRC, Src0RC, Src1RC, Src2RC, NumSrcArgs,
HasModifiers, Src0Mod, Src1Mod, Src2Mod, HasOld>.ret,
- (ins dpp8:$dpp8, FI:$fi));
+ (ins dpp8:$dpp8, DppFI:$fi));
}
class getInsVOP3DPPBase<dag VOP3Base, RegisterOperand OldRC, int NumSrcArgs, bit HasOld> {
@@ -1861,18 +1861,18 @@ class getInsVOP3DPPBase<dag VOP3Base, RegisterOperand OldRC, int NumSrcArgs, bit
class getInsVOP3DPP<dag VOP3Base, RegisterOperand OldRC, int NumSrcArgs, bit HasOld = 1> {
dag ret = !con(getInsVOP3DPPBase<VOP3Base,OldRC,NumSrcArgs,HasOld>.ret,
- (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl));
+ (ins dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
+ DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl));
}
class getInsVOP3DPP16<dag VOP3Base, RegisterOperand OldRC, int NumSrcArgs, bit HasOld = 1> {
dag ret = !con(getInsVOP3DPP<VOP3Base,OldRC,NumSrcArgs,HasOld>.ret,
- (ins FI:$fi));
+ (ins DppFI:$fi));
}
class getInsVOP3DPP8<dag VOP3Base, RegisterOperand OldRC, int NumSrcArgs, bit HasOld = 1> {
dag ret = !con(getInsVOP3DPPBase<VOP3Base,OldRC,NumSrcArgs,HasOld>.ret,
- (ins dpp8:$dpp8, FI:$fi));
+ (ins dpp8:$dpp8, DppFI:$fi));
}
// Ins for SDWA
diff --git a/llvm/lib/Target/AMDGPU/VINTERPInstructions.td b/llvm/lib/Target/AMDGPU/VINTERPInstructions.td
index fc563b7493adff..f84e163b2df037 100644
--- a/llvm/lib/Target/AMDGPU/VINTERPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VINTERPInstructions.td
@@ -78,7 +78,7 @@ def VOP3_VINTERP_F32 : VOPProfile<[f32, f32, f32, f32]> {
Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
clampmod:$clamp,
- wait_exp:$waitexp);
+ WaitEXP:$waitexp);
let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$waitexp";
}
@@ -96,7 +96,7 @@ class VOP3_VINTERP_F16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
clampmod:$clamp, op_sel0:$op_sel,
- wait_exp:$waitexp);
+ WaitEXP:$waitexp);
let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
}
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index ef652fce65482c..920c220fb2c65c 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -399,10 +399,10 @@ class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, un
let OutsDPP = (outs Src0RC32:$vdst);
let InsDPP16 = (ins Src0RC32:$old, Src0RC32:$src0,
- dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl, FI:$fi);
+ dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
+ DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl, DppFI:$fi);
let AsmDPP16 = getAsmDPP16<1, 1, 0>.ret;
- let InsDPP8 = (ins Src0RC32:$old, Src0RC32:$src0, dpp8:$dpp8, FI:$fi);
+ let InsDPP8 = (ins Src0RC32:$old, Src0RC32:$src0, dpp8:$dpp8, DppFI:$fi);
let AsmDPP8 = getAsmDPP8<1, 1, 0>.ret;
let OutsVOP3DPP = (outs Src0RC64:$vdst);
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 27eec64f59a635..eba9bf64884ec8 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -428,9 +428,9 @@ class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, v
let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
- dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
- let InsDPP16 = !con(InsDPP, (ins FI:$fi));
+ dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
+ DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);
+ let InsDPP16 = !con(InsDPP, (ins DppFI:$fi));
let InsVOP3Base = getInsVOP3Base<Src0VOP3DPP, Src1VOP3DPP, RegisterOperand<VGPR_32>, 3,
0, HasModifiers, HasModifiers, HasOMod,
Src0ModVOP3DPP, Src1ModVOP3DPP, Src2Mod, HasOpSel>.ret;
@@ -447,7 +447,7 @@ class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, v
let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
- dpp8:$dpp8, FI:$fi);
+ dpp8:$dpp8, DppFI:$fi);
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
@@ -495,12 +495,12 @@ def VOP_MAC_F16_t16 : VOP_MAC <f16> {
let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret:$src2, // stub argument
- dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
+ dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
+ DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);
let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret:$src2, // stub argument
- dpp8:$dpp8, FI:$fi);
+ dpp8:$dpp8, DppFI:$fi);
let Src2Mod = FP32InputMods; // dummy unused modifiers
let Src2RC64 = VGPRSrc_32; // stub argument
}
@@ -550,13 +550,13 @@ def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], /*EnableClamp=*/
let InsDPP = (ins DstRCDPP:$old,
Src0DPP:$src0,
Src1DPP:$src1,
- dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
- let InsDPP16 = !con(InsDPP, (ins FI:$fi));
+ dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
+ DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);
+ let InsDPP16 = !con(InsDPP, (ins DppFI:$fi));
let InsDPP8 = (ins DstRCDPP:$old,
Src0DPP:$src0,
Src1DPP:$src1,
- dpp8:$dpp8, FI:$fi);
+ dpp8:$dpp8, DppFI:$fi);
let Outs32 = (outs DstRC:$vdst);
let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
let OutsVOP3DPP = Outs64;
@@ -592,13 +592,13 @@ def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableClamp=*/1>
let InsDPP = (ins DstRCDPP:$old,
Src0DPP:$src0,
Src1DPP:$src1,
- dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
- let InsDPP16 = !con(InsDPP, (ins FI:$fi));
+ dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
+ DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);
+ let InsDPP16 = !con(InsDPP, (ins DppFI:$fi));
let InsDPP8 = (ins DstRCDPP:$old,
Src0DPP:$src0,
Src1DPP:$src1,
- dpp8:$dpp8, FI:$fi);
+ dpp8:$dpp8, DppFI:$fi);
let HasExt = 1;
let HasExtDPP = 1;
@@ -643,13 +643,13 @@ class VOP2e_SGPR<list<ValueType> ArgVT> : VOPProfile<ArgVT> {
let InsDPP = (ins DstRCDPP:$old,
FPVRegInputMods:$src0_modifiers, Src0DPP:$src0,
FPVRegInputMods:$src1_modifiers, Src1DPP:$src1,
- dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
- let InsDPP16 = !con(InsDPP, (ins FI:$fi));
+ dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
+ DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);
+ let InsDPP16 = !con(InsDPP, (ins DppFI:$fi));
let InsDPP8 = (ins DstRCDPP:$old,
FPVRegInputMods:$src0_modifiers, Src0DPP:$src0,
FPVRegInputMods:$src1_modifiers, Src1DPP:$src1,
- dpp8:$dpp8, FI:$fi);
+ dpp8:$dpp8, DppFI:$fi);
let Src0ModVOP3DPP = FPVRegInputMods;
let Src1ModVOP3DPP = FPVRegInputMods;
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 14db5221021489..8d965d3b9041d5 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -524,19 +524,19 @@ def VOP3_CVT_PK_F8_F32_Profile : VOP3_Profile<VOP_I32_F32_F32, VOP3_OPSEL> {
FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
FP32InputMods:$src1_modifiers, Src1VOP3DPP:$src1,
VGPR_32:$vdst_in, op_sel0:$op_sel,
- dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
+ dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
+ DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);
let InsVOP3DPP16 = (ins VGPR_32:$old,
FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
FP32InputMods:$src1_modifiers, Src1VOP3DPP:$src1,
VGPR_32:$vdst_in, op_sel0:$op_sel,
- dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl, FI:$fi);
+ dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
+ DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl, DppFI:$fi);
let InsVOP3DPP8 = (ins VGPR_32:$old,
FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
FP32InputMods:$src1_modifiers, Src1VOP3DPP:$src1,
- VGPR_32:$vdst_in, op_sel0:$op_sel, dpp8:$dpp8, FI:$fi);
+ VGPR_32:$vdst_in, op_sel0:$op_sel, dpp8:$dpp8, DppFI:$fi);
let HasClamp = 0;
let HasExtVOP3DPP = 1;
@@ -552,13 +552,13 @@ def VOP3_CVT_SR_F8_F32_Profile : VOP3_Profile<VOPProfile<[i32, f32, i32, f32]>,
FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
FP32InputMods:$src1_modifiers, Src1VOP3DPP:$src1,
FP32InputMods:$src2_modifiers, VGPR_32:$src2,
- op_sel0:$op_sel, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl, FI:$fi);
+ op_sel0:$op_sel, dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
+ DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl, DppFI:$fi);
let InsVOP3DPP8 = (ins VGPR_32:$old,
FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
FP32InputMods:$src1_modifiers, Src1VOP3DPP:$src1,
FP32InputMods:$src2_modifiers, VGPR_32:$src2,
- op_sel0:$op_sel, dpp8:$dpp8, FI:$fi);
+ op_sel0:$op_sel, dpp8:$dpp8, DppFI:$fi);
let HasClamp = 0;
let HasSrc2 = 0;
let HasSrc2Mods = 1;
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 0c7a08cd4bc91f..f74437ed69b188 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -461,13 +461,13 @@ def VOP3P_DOTF8_Profile : VOP3P_Profile<VOPProfile <[f32, i32, i32, f32]>,
let InsVOP3DPP8 = (ins DstRC:$old, VGPR_32:$src0, VRegSrc_32:$src1,
PackedF16InputMods:$src2_modifiers, VRegSrc_32:$src2,
- neg_lo0:$neg_lo, neg_hi0:$neg_hi, dpp8:$dpp8, FI:$fi);
+ neg_lo0:$neg_lo, neg_hi0:$neg_hi, dpp8:$dpp8, DppFI:$fi);
let InsVOP3DPP16 = (ins DstRC:$old, VGPR_32:$src0, VRegSrc_32:$src1,
PackedF16InputMods:$src2_modifiers, VRegSrc_32:$src2,
neg_lo0:$neg_lo, neg_hi0:$neg_hi, dpp_ctrl:$dpp_ctrl,
- row_mask:$row_mask, bank_mask:$bank_mask,
- bound_ctrl:$bound_ctrl, FI:$fi);
+ DppRowMask:$row_mask, DppBankMask:$bank_mask,
+ DppBoundCtrl:$bound_ctrl, DppFI:$fi);
}
multiclass VOP3PDOTF8Inst <string OpName, SDPatternOperator intrinsic_node> {
@@ -547,7 +547,7 @@ class VOPProfileMAI<VOPProfile P, RegisterOperand _SrcRC, RegisterOperand _DstRC
let HasOMod = 0;
let HasModifiers = 0;
let AsmVOP3Base = "$vdst, $src0, $src1, $src2$cbsz$abid$blgp";
- let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, Src2RC64:$src2, cbsz:$cbsz, abid:$abid, blgp:$blgp);
+ let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, Src2RC64:$src2, CBSZ:$cbsz, ABID:$abid, blgp:$blgp);
let InsVOP3Base = Ins64;
// Dst and SrcC cannot partially overlap if SrcC/Dst is bigger than 4 VGPRs.
// We then create two versions of the instruction: with tied dst and src2
@@ -564,7 +564,7 @@ class VOPProfileSMFMAC<VOPProfile P, RegisterOperand _DstRC,
let Src2VT = DstVT;
let Asm64 = " $vdst, $src0, $src1, $idx$cbsz$abid";
let Outs64 = (outs DstRC:$vdst);
- let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, VRegSrc_32:$idx, cbsz:$cbsz, abid:$abid, Src2RC64:$src2);
+ let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, VRegSrc_32:$idx, CBSZ:$cbsz, ABID:$abid, Src2RC64:$src2);
}
def VOPProfileMAI_F32_F32_X4 : VOPProfileMAI<VOP_V4F32_F32_F32_V4F32, AISrc_128_f32, ADst_128>;
@@ -1139,11 +1139,11 @@ multiclass VOP3P_Real_MFMA_gfx940_aliases<string NameFrom, string NameTo, string
def : InstAlias <NameTo # " " # PS_ACD.AsmOperands,
(!cast<VOP3P_Real>(Op # "_gfx940_acd") Pfl_ACD.DstRC:$vdst,
Pfl_ACD.Src0RC64:$src0, Pfl_ACD.Src1RC64:$src1, Pfl_ACD.Src2RC64:$src2,
- cbsz:$cbsz, abid:$abid, blgp:$blgp)>, PredicateControl;
+ CBSZ:$cbsz, ABID:$abid, blgp:$blgp)>, PredicateControl;
def : InstAlias <NameTo # " " # PS_VCD.AsmOperands,
(!cast<VOP3P_Real>(Op # "_gfx940_vcd") Pfl_VCD.DstRC:$vdst,
Pfl_VCD.Src0RC64:$src0, Pfl_VCD.Src1RC64:$src1, Pfl_VCD.Src2RC64:$src2,
- cbsz:$cbsz, abid:$abid, blgp:$blgp)>, PredicateControl;
+ CBSZ:$cbsz, ABID:$abid, blgp:$blgp)>, PredicateControl;
}
}
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index 3ca97f0291e01b..861c9f75e866d5 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -765,8 +765,8 @@ class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType
VOPC_Profile<sched, src0VT, src1VT> {
let AsmDPP = "$src0_modifiers, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
let AsmDPP16 = AsmDPP#"$fi";
- let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, Src1DPP:$src1, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
- let InsDPP16 = !con(InsDPP, (ins FI:$fi));
+ let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, Src1DPP:$src1, dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask, DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);
+ let InsDPP16 = !con(InsDPP, (ins DppFI:$fi));
// DPP8 forbids modifiers and can inherit from VOPC_Profile
let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
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